74 static unsigned findFirstFreeSGPR(CCState &CCInfo) {  in findFirstFreeSGPR()  argument
77     if (!CCInfo.isAllocated(AMDGPU::SGPR0 + Reg)) {  in findFirstFreeSGPR()
2179 void SITargetLowering::allocateSpecialEntryInputVGPRs(CCState &CCInfo,  in allocateSpecialEntryInputVGPRs()  argument
2190     CCInfo.AllocateReg(Reg);  in allocateSpecialEntryInputVGPRs()
2205       CCInfo.AllocateReg(Reg);  in allocateSpecialEntryInputVGPRs()
2219       CCInfo.AllocateReg(Reg);  in allocateSpecialEntryInputVGPRs()
2229 static ArgDescriptor allocateVGPR32Input(CCState &CCInfo, unsigned Mask = ~0u,  in allocateVGPR32Input()  argument
2235   unsigned RegIdx = CCInfo.getFirstUnallocated(ArgVGPRs);  in allocateVGPR32Input()
2238     int64_t Offset = CCInfo.AllocateStack(4, Align(4));  in allocateVGPR32Input()
2244   Reg = CCInfo.AllocateReg(Reg);  in allocateVGPR32Input()
2247   MachineFunction &MF = CCInfo.getMachineFunction();  in allocateVGPR32Input()
2253 static ArgDescriptor allocateSGPR32InputImpl(CCState &CCInfo,  in allocateSGPR32InputImpl()  argument
2257   unsigned RegIdx = CCInfo.getFirstUnallocated(ArgSGPRs);  in allocateSGPR32InputImpl()
2262   Reg = CCInfo.AllocateReg(Reg);  in allocateSGPR32InputImpl()
2265   MachineFunction &MF = CCInfo.getMachineFunction();  in allocateSGPR32InputImpl()
2273 static void allocateFixedSGPRInputImpl(CCState &CCInfo,  in allocateFixedSGPRInputImpl()  argument
2276   Reg = CCInfo.AllocateReg(Reg);  in allocateFixedSGPRInputImpl()
2278   MachineFunction &MF = CCInfo.getMachineFunction();  in allocateFixedSGPRInputImpl()
2282 static void allocateSGPR32Input(CCState &CCInfo, ArgDescriptor &Arg) {  in allocateSGPR32Input()  argument
2284     allocateFixedSGPRInputImpl(CCInfo, &AMDGPU::SGPR_32RegClass,  in allocateSGPR32Input()
2287     Arg = allocateSGPR32InputImpl(CCInfo, &AMDGPU::SGPR_32RegClass, 32);  in allocateSGPR32Input()
2290 static void allocateSGPR64Input(CCState &CCInfo, ArgDescriptor &Arg) {  in allocateSGPR64Input()  argument
2292     allocateFixedSGPRInputImpl(CCInfo, &AMDGPU::SGPR_64RegClass,  in allocateSGPR64Input()
2295     Arg = allocateSGPR32InputImpl(CCInfo, &AMDGPU::SGPR_64RegClass, 16);  in allocateSGPR64Input()
2301   CCState &CCInfo, MachineFunction &MF,  in allocateSpecialInputVGPRs()  argument
2307     Arg = allocateVGPR32Input(CCInfo, Mask);  in allocateSpecialInputVGPRs()
2312     Arg = allocateVGPR32Input(CCInfo, Mask << 10, Arg);  in allocateSpecialInputVGPRs()
2317     Info.setWorkItemIDZ(allocateVGPR32Input(CCInfo, Mask << 20, Arg));  in allocateSpecialInputVGPRs()
2322   CCState &CCInfo, MachineFunction &MF,  in allocateSpecialInputVGPRsFixed()  argument
2324   Register Reg = CCInfo.AllocateReg(AMDGPU::VGPR31);  in allocateSpecialInputVGPRsFixed()
2335   CCState &CCInfo,  in allocateSpecialInputSGPRs()  argument
2344     allocateSGPR64Input(CCInfo, ArgInfo.DispatchPtr);  in allocateSpecialInputSGPRs()
2349     allocateSGPR64Input(CCInfo, ArgInfo.QueuePtr);  in allocateSpecialInputSGPRs()
2354     allocateSGPR64Input(CCInfo, ArgInfo.ImplicitArgPtr);  in allocateSpecialInputSGPRs()
2357     allocateSGPR64Input(CCInfo, ArgInfo.DispatchID);  in allocateSpecialInputSGPRs()
2362     allocateSGPR32Input(CCInfo, ArgInfo.WorkGroupIDX);  in allocateSpecialInputSGPRs()
2365     allocateSGPR32Input(CCInfo, ArgInfo.WorkGroupIDY);  in allocateSpecialInputSGPRs()
2368     allocateSGPR32Input(CCInfo, ArgInfo.WorkGroupIDZ);  in allocateSpecialInputSGPRs()
2371     allocateSGPR32Input(CCInfo, ArgInfo.LDSKernelId);  in allocateSpecialInputSGPRs()
2375 void SITargetLowering::allocateHSAUserSGPRs(CCState &CCInfo,  in allocateHSAUserSGPRs()  argument
2383     CCInfo.AllocateReg(ImplicitBufferPtrReg);  in allocateHSAUserSGPRs()
2390     CCInfo.AllocateReg(PrivateSegmentBufferReg);  in allocateHSAUserSGPRs()
2396     CCInfo.AllocateReg(DispatchPtrReg);  in allocateHSAUserSGPRs()
2404     CCInfo.AllocateReg(QueuePtrReg);  in allocateHSAUserSGPRs()
2410     CCInfo.AllocateReg(InputPtrReg);  in allocateHSAUserSGPRs()
2419     CCInfo.AllocateReg(DispatchIDReg);  in allocateHSAUserSGPRs()
2425     CCInfo.AllocateReg(FlatScratchInitReg);  in allocateHSAUserSGPRs()
2435     CCState &CCInfo, SmallVectorImpl<CCValAssign> &ArgLocs,  in allocatePreloadKernArgSGPRs()  argument
2493         CCInfo.AllocateReg(Reg);  in allocatePreloadKernArgSGPRs()
2501 void SITargetLowering::allocateLDSKernelId(CCState &CCInfo, MachineFunction &MF,  in allocateLDSKernelId()  argument
2508     CCInfo.AllocateReg(Reg);  in allocateLDSKernelId()
2513 void SITargetLowering::allocateSystemSGPRs(CCState &CCInfo,  in allocateSystemSGPRs()  argument
2538       CCInfo.AllocateReg(Reg);  in allocateSystemSGPRs()
2546       CCInfo.AllocateReg(Reg);  in allocateSystemSGPRs()
2552       CCInfo.AllocateReg(Reg);  in allocateSystemSGPRs()
2558       CCInfo.AllocateReg(Reg);  in allocateSystemSGPRs()
2565     CCInfo.AllocateReg(Reg);  in allocateSystemSGPRs()
2579         PrivateSegmentWaveByteOffsetReg = findFirstFreeSGPR(CCInfo);  in allocateSystemSGPRs()
2586     CCInfo.AllocateReg(PrivateSegmentWaveByteOffsetReg);  in allocateSystemSGPRs()
2748   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,  in LowerFormalArguments()  local
2787       CCInfo.AllocateReg(AMDGPU::VGPR0);  in LowerFormalArguments()
2788       CCInfo.AllocateReg(AMDGPU::VGPR1);  in LowerFormalArguments()
2813     analyzeFormalArgumentsCompute(CCInfo, Ins);  in LowerFormalArguments()
2816     allocateSpecialEntryInputVGPRs(CCInfo, MF, *TRI, *Info);  in LowerFormalArguments()
2817     allocateHSAUserSGPRs(CCInfo, MF, *TRI, *Info);  in LowerFormalArguments()
2820       allocatePreloadKernArgSGPRs(CCInfo, ArgLocs, Ins, MF, *TRI, *Info);  in LowerFormalArguments()
2822     allocateLDSKernelId(CCInfo, MF, *TRI, *Info);  in LowerFormalArguments()
2825     allocateSpecialInputVGPRsFixed(CCInfo, MF, *TRI, *Info);  in LowerFormalArguments()
2829       CCInfo.AllocateReg(Info->getScratchRSrcReg());  in LowerFormalArguments()
2831     allocateSpecialInputSGPRs(CCInfo, MF, *TRI, *Info);  in LowerFormalArguments()
2836     CCInfo.AnalyzeFormalArguments(Splits, AssignFn);  in LowerFormalArguments()
3036     allocateSystemSGPRs(CCInfo, MF, *Info, CallConv, IsGraphics);  in LowerFormalArguments()
3042   unsigned StackArgSize = CCInfo.getStackSize();  in LowerFormalArguments()
3063   CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);  in CanLowerReturn()  local
3064   if (!CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg)))  in CanLowerReturn()
3071     if (CCInfo.isAllocated(AMDGPU::VGPR_32RegClass.getRegister(i)))  in CanLowerReturn()
3101   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,  in LowerReturn()  local
3105   CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));  in LowerReturn()
3181   CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,  in LowerCallResult()  local
3183   CCInfo.AnalyzeCallResult(Ins, RetCC);  in LowerCallResult()
3232     CCState &CCInfo,  in passSpecialInputs()  argument
3321       if (!CCInfo.AllocateReg(OutgoingArg->getRegister()))  in passSpecialInputs()
3325           CCInfo.AllocateStack(ArgVT.getStoreSize(), Align(4));  in passSpecialInputs()
3413     CCInfo.AllocateReg(OutgoingArg->getRegister());  in passSpecialInputs()
3415     unsigned SpecialArgOffset = CCInfo.AllocateStack(4, Align(4));  in passSpecialInputs()
3503   CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs, Ctx);  in isEligibleForTailCallOptimization()  local
3505   CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, IsVarArg));  in isEligibleForTailCallOptimization()
3511   if (CCInfo.getStackSize() > FuncInfo->getBytesInStackArgArea())  in isEligibleForTailCallOptimization()
3621   CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());  in LowerCall()  local
3626     passSpecialInputs(CLI, CCInfo, *Info, RegsToPass, MemOpChains, Chain);  in LowerCall()
3629   CCInfo.AnalyzeCallOperands(Outs, AssignFn);  in LowerCall()
3632   unsigned NumBytes = CCInfo.getStackSize();  in LowerCall()