549   Register ScratchRsrcReg = MFI->getScratchRSrcReg();  in getEntryFunctionReservedScratchRsrcReg()  local
551   if (!ScratchRsrcReg || (!MRI.isPhysRegUsed(ScratchRsrcReg) &&  in getEntryFunctionReservedScratchRsrcReg()
556       ScratchRsrcReg != TRI->reservedPrivateSegmentBufferReg(MF))  in getEntryFunctionReservedScratchRsrcReg()
557     return ScratchRsrcReg;  in getEntryFunctionReservedScratchRsrcReg()
581       MRI.replaceRegWith(ScratchRsrcReg, Reg);  in getEntryFunctionReservedScratchRsrcReg()
587   return ScratchRsrcReg;  in getEntryFunctionReservedScratchRsrcReg()
628   Register ScratchRsrcReg;  in emitEntryFunctionPrologue()  local
630     ScratchRsrcReg = getEntryFunctionReservedScratchRsrcReg(MF);  in emitEntryFunctionPrologue()
633   if (ScratchRsrcReg) {  in emitEntryFunctionPrologue()
636         OtherBB.addLiveIn(ScratchRsrcReg);  in emitEntryFunctionPrologue()
647     if (ScratchRsrcReg && PreloadedScratchRsrcReg) {  in emitEntryFunctionPrologue()
667       TRI->isSubRegisterEq(ScratchRsrcReg, PreloadedScratchWaveOffsetReg)) {  in emitEntryFunctionPrologue()
675           !TRI->isSubRegisterEq(ScratchRsrcReg, Reg) && GITPtrLoReg != Reg) {  in emitEntryFunctionPrologue()
705   if ((NeedsFlatScratchInit || ScratchRsrcReg) &&  in emitEntryFunctionPrologue()
715   if (ScratchRsrcReg) {  in emitEntryFunctionPrologue()
718                                          ScratchRsrcReg, ScratchWaveOffsetReg);  in emitEntryFunctionPrologue()
726     Register ScratchRsrcReg, Register ScratchWaveOffsetReg) const {  in emitEntryFunctionScratchRsrcRegSetup()  argument
737     Register Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);  in emitEntryFunctionScratchRsrcRegSetup()
738     Register Rsrc03 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);  in emitEntryFunctionScratchRsrcRegSetup()
754     BuildMI(MBB, I, DL, LoadDwordX4, ScratchRsrcReg)  in emitEntryFunctionScratchRsrcRegSetup()
758       .addReg(ScratchRsrcReg, RegState::ImplicitDefine)  in emitEntryFunctionScratchRsrcRegSetup()
778     Register Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2);  in emitEntryFunctionScratchRsrcRegSetup()
779     Register Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);  in emitEntryFunctionScratchRsrcRegSetup()
785       Register Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);  in emitEntryFunctionScratchRsrcRegSetup()
792           .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
807           .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
813       Register Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);  in emitEntryFunctionScratchRsrcRegSetup()
814       Register Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);  in emitEntryFunctionScratchRsrcRegSetup()
818         .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
822         .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
827       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
831       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
835     if (ScratchRsrcReg != PreloadedScratchRsrcReg) {  in emitEntryFunctionScratchRsrcRegSetup()
836       BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchRsrcReg)  in emitEntryFunctionScratchRsrcRegSetup()
850   Register ScratchRsrcSub0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);  in emitEntryFunctionScratchRsrcRegSetup()
851   Register ScratchRsrcSub1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);  in emitEntryFunctionScratchRsrcRegSetup()
858       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
862       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()