Lines Matching refs:MF
73 MachineFunction &MF, LiveRegUnits &LiveUnits, Register SGPR, in getVGPRSpillLaneOrTempRegister() argument
76 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); in getVGPRSpillLaneOrTempRegister()
77 MachineFrameInfo &FrameInfo = MF.getFrameInfo(); in getVGPRSpillLaneOrTempRegister()
79 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in getVGPRSpillLaneOrTempRegister()
91 ScratchSGPR = findUnusedRegister(MF.getRegInfo(), LiveUnits, RC); in getVGPRSpillLaneOrTempRegister()
98 MFI->allocateSGPRSpillToVGPRLane(MF, FI, /*SpillToPhysVGPRLane=*/true, in getVGPRSpillLaneOrTempRegister()
112 MF.getFrameInfo().RemoveStackObject(FI); in getVGPRSpillLaneOrTempRegister()
136 LiveRegUnits &LiveUnits, MachineFunction &MF, in buildPrologSpill() argument
144 MachineFrameInfo &FrameInfo = MF.getFrameInfo(); in buildPrologSpill()
145 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI); in buildPrologSpill()
146 MachineMemOperand *MMO = MF.getMachineMemOperand( in buildPrologSpill()
160 LiveRegUnits &LiveUnits, MachineFunction &MF, in buildEpilogRestore() argument
168 MachineFrameInfo &FrameInfo = MF.getFrameInfo(); in buildEpilogRestore()
169 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI); in buildEpilogRestore()
170 MachineMemOperand *MMO = MF.getMachineMemOperand( in buildEpilogRestore()
180 MachineFunction *MF = MBB.getParent(); in buildGitPtr() local
181 const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>(); in buildGitPtr()
195 Register GitPtrLo = MFI->getGITPtrLoReg(*MF); in buildGitPtr()
196 MF->getRegInfo().addLiveIn(GitPtrLo); in buildGitPtr()
204 MachineFunction &MF, MachineBasicBlock &MBB, in initLiveUnits() argument
227 MachineFunction &MF; member in llvm::PrologEpilogSGPRSpillBuilder
243 MachineRegisterInfo &MRI = MF.getRegInfo(); in saveToMemory()
246 initLiveUnits(LiveUnits, TRI, FuncInfo, MF, MBB, MI, /*IsProlog*/ true); in saveToMemory()
260 buildPrologSpill(ST, TRI, *FuncInfo, LiveUnits, MF, MBB, MI, DL, TmpVGPR, in saveToMemory()
293 MachineRegisterInfo &MRI = MF.getRegInfo(); in restoreFromMemory()
295 initLiveUnits(LiveUnits, TRI, FuncInfo, MF, MBB, MI, /*IsProlog*/ false); in restoreFromMemory()
306 buildEpilogRestore(ST, TRI, *FuncInfo, LiveUnits, MF, MBB, MI, DL, in restoreFromMemory()
344 : MI(MI), MBB(MBB), MF(*MBB.getParent()), in PrologEpilogSGPRSpillBuilder()
345 ST(MF.getSubtarget<GCNSubtarget>()), MFI(MF.getFrameInfo()), in PrologEpilogSGPRSpillBuilder()
346 FuncInfo(MF.getInfo<SIMachineFunctionInfo>()), TII(TII), TRI(TRI), in PrologEpilogSGPRSpillBuilder()
383 MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I, in emitEntryFunctionFlatScratchInit() argument
385 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitEntryFunctionFlatScratchInit()
388 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); in emitEntryFunctionFlatScratchInit()
410 MachineRegisterInfo &MRI = MF.getRegInfo(); in emitEntryFunctionFlatScratchInit()
412 ArrayRef<MCPhysReg> AllSGPR64s = TRI->getAllSGPR64(MF); in emitEntryFunctionFlatScratchInit()
416 Register GITPtrLoReg = MFI->getGITPtrLoReg(MF); in emitEntryFunctionFlatScratchInit()
435 auto *MMO = MF.getMachineMemOperand( in emitEntryFunctionFlatScratchInit()
441 MF.getFunction().getCallingConv() == CallingConv::AMDGPU_CS ? 16 : 0; in emitEntryFunctionFlatScratchInit()
442 const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>(); in emitEntryFunctionFlatScratchInit()
461 MachineRegisterInfo &MRI = MF.getRegInfo(); in emitEntryFunctionFlatScratchInit()
539 MachineFunction &MF) const { in getEntryFunctionReservedScratchRsrcReg()
541 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in getEntryFunctionReservedScratchRsrcReg()
544 MachineRegisterInfo &MRI = MF.getRegInfo(); in getEntryFunctionReservedScratchRsrcReg()
545 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); in getEntryFunctionReservedScratchRsrcReg()
552 allStackObjectsAreDead(MF.getFrameInfo()))) in getEntryFunctionReservedScratchRsrcReg()
556 ScratchRsrcReg != TRI->reservedPrivateSegmentBufferReg(MF)) in getEntryFunctionReservedScratchRsrcReg()
569 ArrayRef<MCPhysReg> AllSGPR128s = TRI->getAllSGPR128(MF); in getEntryFunctionReservedScratchRsrcReg()
574 Register GITPtrLoReg = MFI->getGITPtrLoReg(MF); in getEntryFunctionReservedScratchRsrcReg()
594 void SIFrameLowering::emitEntryFunctionPrologue(MachineFunction &MF, in emitEntryFunctionPrologue() argument
596 assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported"); in emitEntryFunctionPrologue()
609 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); in emitEntryFunctionPrologue()
610 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitEntryFunctionPrologue()
613 MachineRegisterInfo &MRI = MF.getRegInfo(); in emitEntryFunctionPrologue()
614 const Function &F = MF.getFunction(); in emitEntryFunctionPrologue()
615 MachineFrameInfo &FrameInfo = MF.getFrameInfo(); in emitEntryFunctionPrologue()
630 ScratchRsrcReg = getEntryFunctionReservedScratchRsrcReg(MF); in emitEntryFunctionPrologue()
634 for (MachineBasicBlock &OtherBB : MF) { in emitEntryFunctionPrologue()
668 ArrayRef<MCPhysReg> AllSGPRs = TRI->getAllSGPR32(MF); in emitEntryFunctionPrologue()
672 Register GITPtrLoReg = MFI->getGITPtrLoReg(MF); in emitEntryFunctionPrologue()
687 if (requiresStackPointerReference(MF)) { in emitEntryFunctionPrologue()
694 if (hasFP(MF)) { in emitEntryFunctionPrologue()
712 emitEntryFunctionFlatScratchInit(MF, MBB, I, DL, ScratchWaveOffsetReg); in emitEntryFunctionPrologue()
716 emitEntryFunctionScratchRsrcRegSetup(MF, MBB, I, DL, in emitEntryFunctionPrologue()
724 MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I, in emitEntryFunctionScratchRsrcRegSetup() argument
728 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitEntryFunctionScratchRsrcRegSetup()
731 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); in emitEntryFunctionScratchRsrcRegSetup()
732 const Function &Fn = MF.getFunction(); in emitEntryFunctionScratchRsrcRegSetup()
746 auto MMO = MF.getMachineMemOperand(PtrInfo, in emitEntryFunctionScratchRsrcRegSetup()
752 const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>(); in emitEntryFunctionScratchRsrcRegSetup()
787 if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) { in emitEntryFunctionScratchRsrcRegSetup()
797 auto MMO = MF.getMachineMemOperand( in emitEntryFunctionScratchRsrcRegSetup()
809 MF.getRegInfo().addLiveIn(MFI->getImplicitBufferPtrUserSGPR()); in emitEntryFunctionScratchRsrcRegSetup()
882 MachineFunction &MF, in buildScratchExecCopy() argument
888 MachineRegisterInfo &MRI = MF.getRegInfo(); in buildScratchExecCopy()
889 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in buildScratchExecCopy()
892 SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>(); in buildScratchExecCopy()
894 initLiveUnits(LiveUnits, TRI, FuncInfo, MF, MBB, MBBI, IsProlog); in buildScratchExecCopy()
916 MachineFunction &MF, MachineBasicBlock &MBB, in emitCSRSpillStores() argument
919 SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>(); in emitCSRSpillStores()
920 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitCSRSpillStores()
929 FuncInfo->splitWWMSpillRegisters(MF, WWMCalleeSavedRegs, WWMScratchRegs); in emitCSRSpillStores()
932 buildScratchExecCopy(LiveUnits, MF, MBB, MBBI, DL, in emitCSRSpillStores()
940 buildPrologSpill(ST, TRI, *FuncInfo, LiveUnits, MF, MBB, MBBI, DL, in emitCSRSpillStores()
951 ScratchExecCopy = buildScratchExecCopy(LiveUnits, MF, MBB, MBBI, DL, in emitCSRSpillStores()
988 for (MachineBasicBlock &MBB : MF) { in emitCSRSpillStores()
1002 MachineFunction &MF, MachineBasicBlock &MBB, in emitCSRSpillRestores() argument
1005 const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>(); in emitCSRSpillRestores()
1006 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitCSRSpillRestores()
1032 FuncInfo->splitWWMSpillRegisters(MF, WWMCalleeSavedRegs, WWMScratchRegs); in emitCSRSpillRestores()
1035 buildScratchExecCopy(LiveUnits, MF, MBB, MBBI, DL, in emitCSRSpillRestores()
1043 buildEpilogRestore(ST, TRI, *FuncInfo, LiveUnits, MF, MBB, MBBI, DL, in emitCSRSpillRestores()
1054 ScratchExecCopy = buildScratchExecCopy(LiveUnits, MF, MBB, MBBI, DL, in emitCSRSpillRestores()
1069 void SIFrameLowering::emitPrologue(MachineFunction &MF, in emitPrologue() argument
1071 SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>(); in emitPrologue()
1073 emitEntryFunctionPrologue(MF, MBB); in emitPrologue()
1077 MachineFrameInfo &MFI = MF.getFrameInfo(); in emitPrologue()
1078 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitPrologue()
1081 MachineRegisterInfo &MRI = MF.getRegInfo(); in emitPrologue()
1086 TRI.hasBasePointer(MF) ? TRI.getBaseRegister() : Register(); in emitPrologue()
1097 bool UseSP = requiresStackPointerReference(MF); in emitPrologue()
1111 if (TRI.hasStackRealignment(MF)) in emitPrologue()
1115 if (!HasFP && !hasFP(MF)) { in emitPrologue()
1117 emitCSRSpillStores(MF, MBB, MBBI, DL, LiveUnits, in emitPrologue()
1125 initLiveUnits(LiveUnits, TRI, FuncInfo, MF, MBB, MBBI, /*IsProlog*/ true); in emitPrologue()
1171 } else if ((HasFP = hasFP(MF))) { in emitPrologue()
1179 emitCSRSpillStores(MF, MBB, MBBI, DL, LiveUnits, FramePtrReg, in emitPrologue()
1189 if ((HasBP = TRI.hasBasePointer(MF))) { in emitPrologue()
1221 void SIFrameLowering::emitEpilogue(MachineFunction &MF, in emitEpilogue() argument
1223 const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>(); in emitEpilogue()
1227 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitEpilogue()
1230 MachineRegisterInfo &MRI = MF.getRegInfo(); in emitEpilogue()
1244 const MachineFrameInfo &MFI = MF.getFrameInfo(); in emitEpilogue()
1261 initLiveUnits(LiveUnits, TRI, FuncInfo, MF, MBB, MBBI, /*IsProlog*/ false); in emitEpilogue()
1273 emitCSRSpillRestores(MF, MBB, MBBI, DL, LiveUnits, FramePtrReg, in emitEpilogue()
1277 if (RoundedSize != 0 && hasFP(MF)) { in emitEpilogue()
1296 emitCSRSpillRestores(MF, MBB, MBBI, DL, LiveUnits, StackPtrReg, in emitEpilogue()
1302 static bool allSGPRSpillsAreDead(const MachineFunction &MF) { in allSGPRSpillsAreDead() argument
1303 const MachineFrameInfo &MFI = MF.getFrameInfo(); in allSGPRSpillsAreDead()
1304 const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>(); in allSGPRSpillsAreDead()
1318 StackOffset SIFrameLowering::getFrameIndexReference(const MachineFunction &MF, in getFrameIndexReference() argument
1321 const SIRegisterInfo *RI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo(); in getFrameIndexReference()
1323 FrameReg = RI->getFrameRegister(MF); in getFrameIndexReference()
1324 return StackOffset::getFixed(MF.getFrameInfo().getObjectOffset(FI)); in getFrameIndexReference()
1328 MachineFunction &MF, in processFunctionBeforeFrameFinalized() argument
1330 MachineFrameInfo &MFI = MF.getFrameInfo(); in processFunctionBeforeFrameFinalized()
1332 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in processFunctionBeforeFrameFinalized()
1335 MachineRegisterInfo &MRI = MF.getRegInfo(); in processFunctionBeforeFrameFinalized()
1336 SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>(); in processFunctionBeforeFrameFinalized()
1342 FuncInfo->isChainFunction() && !MF.getFrameInfo().hasTailCall(); in processFunctionBeforeFrameFinalized()
1346 FuncInfo->allocateWWMSpill(MF, Reg, TRI->getSpillSize(*RC), in processFunctionBeforeFrameFinalized()
1361 for (MachineBasicBlock &MBB : MF) { in processFunctionBeforeFrameFinalized()
1375 if (FuncInfo->allocateVGPRSpillToAGPR(MF, FI, in processFunctionBeforeFrameFinalized()
1397 for (MachineBasicBlock &MBB : MF) { in processFunctionBeforeFrameFinalized()
1426 assert(allSGPRSpillsAreDead(MF) && in processFunctionBeforeFrameFinalized()
1441 allocateScavengingFrameIndexesNearIncomingSP(MF)) { in processFunctionBeforeFrameFinalized()
1448 MachineFunction &MF, RegScavenger *RS) const { in processFunctionBeforeFrameIndicesReplaced() argument
1449 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in processFunctionBeforeFrameIndicesReplaced()
1451 MachineRegisterInfo &MRI = MF.getRegInfo(); in processFunctionBeforeFrameIndicesReplaced()
1452 SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>(); in processFunctionBeforeFrameIndicesReplaced()
1461 TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF); in processFunctionBeforeFrameIndicesReplaced()
1476 TRI->findUnusedRegister(MRI, &AMDGPU::SGPR_64RegClass, MF); in processFunctionBeforeFrameIndicesReplaced()
1490 MachineFunction &MF, BitVector &SavedVGPRs, in determinePrologEpilogSGPRSaves() argument
1492 MachineFrameInfo &FrameInfo = MF.getFrameInfo(); in determinePrologEpilogSGPRSaves()
1493 MachineRegisterInfo &MRI = MF.getRegInfo(); in determinePrologEpilogSGPRSaves()
1494 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); in determinePrologEpilogSGPRSaves()
1495 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in determinePrologEpilogSGPRSaves()
1501 const MCPhysReg *CSRegs = MF.getRegInfo().getCalleeSavedRegs(); in determinePrologEpilogSGPRSaves()
1520 getVGPRSpillLaneOrTempRegister(MF, LiveUnits, ReservedReg, RC, in determinePrologEpilogSGPRSaves()
1537 if (WillHaveFP || hasFP(MF)) { in determinePrologEpilogSGPRSaves()
1541 getVGPRSpillLaneOrTempRegister(MF, LiveUnits, FramePtrReg); in determinePrologEpilogSGPRSaves()
1544 if (TRI->hasBasePointer(MF)) { in determinePrologEpilogSGPRSaves()
1548 getVGPRSpillLaneOrTempRegister(MF, LiveUnits, BasePtrReg); in determinePrologEpilogSGPRSaves()
1553 void SIFrameLowering::determineCalleeSaves(MachineFunction &MF, in determineCalleeSaves() argument
1556 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); in determineCalleeSaves()
1561 if (MFI->isChainFunction() && !MF.getFrameInfo().hasTailCall()) in determineCalleeSaves()
1564 MFI->shiftSpillPhysVGPRsToLowestRange(MF); in determineCalleeSaves()
1566 TargetFrameLowering::determineCalleeSaves(MF, SavedVGPRs, RS); in determineCalleeSaves()
1570 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in determineCalleeSaves()
1576 for (MachineBasicBlock &MBB : MF) { in determineCalleeSaves()
1587 MFI->allocateWWMSpill(MF, MI.getOperand(0).getReg()); in determineCalleeSaves()
1589 MFI->allocateWWMSpill(MF, MI.getOperand(1).getReg()); in determineCalleeSaves()
1623 determinePrologEpilogSGPRSaves(MF, SavedVGPRs, NeedExecCopyReservedReg); in determineCalleeSaves()
1631 for (MachineBasicBlock &MBB : MF) { in determineCalleeSaves()
1639 void SIFrameLowering::determineCalleeSavesSGPR(MachineFunction &MF, in determineCalleeSavesSGPR() argument
1642 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); in determineCalleeSavesSGPR()
1643 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); in determineCalleeSavesSGPR()
1647 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in determineCalleeSavesSGPR()
1661 MachineFrameInfo &FrameInfo = MF.getFrameInfo(); in determineCalleeSavesSGPR()
1666 if (WillHaveFP || hasFP(MF)) in determineCalleeSavesSGPR()
1675 const MachineRegisterInfo &MRI = MF.getRegInfo(); in determineCalleeSavesSGPR()
1676 Register RetAddrReg = TRI->getReturnAddressReg(MF); in determineCalleeSavesSGPR()
1685 MachineFunction &MF, const TargetRegisterInfo *TRI, in assignCalleeSavedSpillSlots() argument
1690 const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>(); in assignCalleeSavedSpillSlots()
1691 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in assignCalleeSavedSpillSlots()
1725 const MachineFunction &MF) const { in allocateScavengingFrameIndexesNearIncomingSP()
1727 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in allocateScavengingFrameIndexesNearIncomingSP()
1728 const MachineFrameInfo &MFI = MF.getFrameInfo(); in allocateScavengingFrameIndexesNearIncomingSP()
1730 uint64_t EstStackSize = MFI.estimateStackSize(MF); in allocateScavengingFrameIndexesNearIncomingSP()
1753 MachineFunction &MF, in eliminateCallFramePseudoInstr() argument
1760 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in eliminateCallFramePseudoInstr()
1767 if (!hasReservedCallFrame(MF)) { in eliminateCallFramePseudoInstr()
1770 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); in eliminateCallFramePseudoInstr()
1801 bool SIFrameLowering::hasFP(const MachineFunction &MF) const { in hasFP()
1802 const MachineFrameInfo &MFI = MF.getFrameInfo(); in hasFP()
1807 !MF.getInfo<SIMachineFunctionInfo>()->isEntryFunction() && in hasFP()
1808 !MF.getInfo<SIMachineFunctionInfo>()->isChainFunction()) { in hasFP()
1818 MF.getSubtarget<GCNSubtarget>().getRegisterInfo()->hasStackRealignment( in hasFP()
1819 MF) || in hasFP()
1820 MF.getTarget().Options.DisableFramePointerElim(MF); in hasFP()
1831 const MachineFunction &MF) const { in requiresStackPointerReference()
1833 assert((MF.getInfo<SIMachineFunctionInfo>()->isEntryFunction() || in requiresStackPointerReference()
1834 MF.getInfo<SIMachineFunctionInfo>()->isChainFunction()) && in requiresStackPointerReference()
1837 const MachineFrameInfo &MFI = MF.getFrameInfo(); in requiresStackPointerReference()