658   MachineInstr *Def = MRI->getVRegDef(UseReg);  in getRegSeqInit()  local
659   if (!Def || !Def->isRegSequence())  in getRegSeqInit()
662   for (unsigned I = 1, E = Def->getNumExplicitOperands(); I < E; I += 2) {  in getRegSeqInit()
663     MachineOperand *Sub = &Def->getOperand(I);  in getRegSeqInit()
681     Defs.emplace_back(Sub, Def->getOperand(I + 1).getImm());  in getRegSeqInit()
715   MachineInstr *Def = MRI->getVRegDef(UseReg);  in tryToFoldACImm()  local
717   if (!UseOp.getSubReg() && Def && TII->isFoldableCopy(*Def)) {  in tryToFoldACImm()
718     MachineOperand &DefOp = Def->getOperand(1);  in tryToFoldACImm()
905           MachineOperand *Def = Defs[I].first;  in foldOperand()  local
907           if (Def->isImm() &&  in foldOperand()
908               TII->isInlineConstant(*Def, AMDGPU::OPERAND_REG_INLINE_C_INT32)) {  in foldOperand()
909             int64_t Imm = Def->getImm();  in foldOperand()
915           } else if (Def->isReg() && TRI->isAGPR(*MRI, Def->getReg())) {  in foldOperand()
916             auto Src = getRegSubRegPair(*Def);  in foldOperand()
917             Def->setIsKill(false);  in foldOperand()
924               B.addReg(Src.Reg, Def->isUndef() ? RegState::Undef : 0,  in foldOperand()
928             assert(Def->isReg());  in foldOperand()
929             Def->setIsKill(false);  in foldOperand()
930             auto Src = getRegSubRegPair(*Def);  in foldOperand()
939               BuildMI(MBB, UseMI, DL, TII->get(AMDGPU::COPY), Tmp).add(*Def);  in foldOperand()
950               BuildMI(MBB, UseMI, DL, TII->get(AMDGPU::COPY), Vgpr).add(*Def);  in foldOperand()
1178   MachineInstr *Def = MRI->getVRegDef(Op.getReg());  in getImmOrMaterializedImm()  local
1179   if (Def && Def->isMoveImmediate()) {  in getImmOrMaterializedImm()
1180     MachineOperand &ImmSrc = Def->getOperand(1);  in getImmOrMaterializedImm()
1544   MachineInstr *Def = MRI->getVRegDef(ClampSrc->getReg());  in tryFoldClamp()  local
1547   if (TII->getClampMask(*Def) != TII->getClampMask(MI))  in tryFoldClamp()
1550   MachineOperand *DefClamp = TII->getNamedOperand(*Def, AMDGPU::OpName::clamp);  in tryFoldClamp()
1554   LLVM_DEBUG(dbgs() << "Folding clamp " << *DefClamp << " into " << *Def);  in tryFoldClamp()
1558   MRI->replaceRegWith(MI.getOperand(0).getReg(), Def->getOperand(0).getReg());  in tryFoldClamp()
1564   if (TII->convertToThreeAddress(*Def, nullptr, nullptr))  in tryFoldClamp()
1565     Def->eraseFromParent();  in tryFoldClamp()
1705   MachineInstr *Def = MRI->getVRegDef(RegOp->getReg());  in tryFoldOMod()  local
1706   MachineOperand *DefOMod = TII->getNamedOperand(*Def, AMDGPU::OpName::omod);  in tryFoldOMod()
1712   if (TII->hasModifiersSet(*Def, AMDGPU::OpName::clamp))  in tryFoldOMod()
1715   LLVM_DEBUG(dbgs() << "Folding omod " << MI << " into " << *Def);  in tryFoldOMod()
1718   MRI->replaceRegWith(MI.getOperand(0).getReg(), Def->getOperand(0).getReg());  in tryFoldOMod()
1724   if (TII->convertToThreeAddress(*Def, nullptr, nullptr))  in tryFoldOMod()
1725     Def->eraseFromParent();  in tryFoldOMod()
1744   for (auto &Def : Defs) {  in tryFoldRegSequence()  local
1745     const auto *Op = Def.first;  in tryFoldRegSequence()
1784     MachineOperand *Def = Defs[I].first;  in tryFoldRegSequence()  local
1785     Def->setIsKill(false);  in tryFoldRegSequence()
1786     if (TRI->isAGPR(*MRI, Def->getReg())) {  in tryFoldRegSequence()
1787       RS.add(*Def);  in tryFoldRegSequence()
1789       MachineInstr *SubDef = MRI->getVRegDef(Def->getReg());  in tryFoldRegSequence()
1791       RS.addReg(SubDef->getOperand(1).getReg(), 0, Def->getSubReg());  in tryFoldRegSequence()
1927     if (MachineInstr *Def = MRI->getVRegDef(Reg)) {  in tryFoldPhiAGPR()  local
1931       if (Def->isCopy()) {  in tryFoldPhiAGPR()
1934         if (isAGPRCopy(*TRI, *MRI, *Def, AGPRSrc, AGPRSubReg)) {  in tryFoldPhiAGPR()
1946         MachineOperand &CopyIn = Def->getOperand(1);  in tryFoldPhiAGPR()
1952       InsertMBB = Def->getParent();  in tryFoldPhiAGPR()
1953       InsertPt = InsertMBB->SkipPHIsLabelsAndDebug(++Def->getIterator());  in tryFoldPhiAGPR()
1990   MachineOperand &Def = MI.getOperand(0);  in tryFoldLoad()  local
1991   if (!Def.isDef())  in tryFoldLoad()
1994   Register DefReg = Def.getReg();  in tryFoldLoad()
2025   if (!TII->isOperandLegal(MI, 0, &Def)) {  in tryFoldLoad()
2103     MachineInstr *Def = MRI->getVRegDef(Reg);  in tryOptimizeAGPRPhis()  local
2104     MachineBasicBlock *DefMBB = Def->getParent();  in tryOptimizeAGPRPhis()
2112         BuildMI(*DefMBB, ++Def->getIterator(), Def->getDebugLoc(),  in tryOptimizeAGPRPhis()
2118     BuildMI(*DefMBB, ++VGPRCopy->getIterator(), Def->getDebugLoc(),  in tryOptimizeAGPRPhis()