192   Register DstReg = Copy.getOperand(0).getReg();  in getCopyRegClasses()  local
202   const TargetRegisterClass *DstRC = DstReg.isVirtual()  in getCopyRegClasses()
203                                          ? MRI.getRegClass(DstReg)  in getCopyRegClasses()
204                                          : TRI.getPhysRegBaseClass(DstReg);  in getCopyRegClasses()
228   Register DstReg = MI.getOperand(0).getReg();  in tryChangeVGPRtoSGPRinCopy()  local
230   if (!SrcReg.isVirtual() || !DstReg.isVirtual())  in tryChangeVGPRtoSGPRinCopy()
233   for (const auto &MO : MRI.reg_nodbg_operands(DstReg)) {  in tryChangeVGPRtoSGPRinCopy()
247   MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg)));  in tryChangeVGPRtoSGPRinCopy()
270   Register DstReg = MI.getOperand(0).getReg();  in foldVGPRCopyIntoRegSequence()  local
271   if (!TRI->isSGPRClass(MRI.getRegClass(DstReg)))  in foldVGPRCopyIntoRegSequence()
274   if (!MRI.hasOneUse(DstReg))  in foldVGPRCopyIntoRegSequence()
277   MachineInstr &CopyUse = *MRI.use_instr_begin(DstReg);  in foldVGPRCopyIntoRegSequence()
299   MRI.setRegClass(DstReg, DstRC);  in foldVGPRCopyIntoRegSequence()
844     MachineOperand &MaybeVGPRConstMO, Register DstReg,  in tryMoveVGPRConstToSGPR()  argument
861           TII->get(MoveOp), DstReg)  in tryMoveVGPRConstToSGPR()
865   MaybeVGPRConstMO.setReg(DstReg);  in tryMoveVGPRConstToSGPR()
871   Register DstReg = MI.getOperand(0).getReg();  in lowerSpecialCase()  local
873   if (!DstReg.isVirtual()) {  in lowerSpecialCase()
878     if (DstReg == AMDGPU::M0 &&  in lowerSpecialCase()
886     } else if (tryMoveVGPRConstToSGPR(MI.getOperand(1), DstReg, MI.getParent(),  in lowerSpecialCase()
914   Register DstReg = MI->getOperand(0).getReg();  in analyzeVGPRToSGPRCopy()  local
915   const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);  in analyzeVGPRToSGPRCopy()
1062     Register DstReg = MI->getOperand(0).getReg();  in lowerVGPR2SGPRCopies()  local
1071                          TII->get(AMDGPU::V_READFIRSTLANE_B32), DstReg);  in lowerVGPR2SGPRCopies()
1075                          TII->get(AMDGPU::V_READFIRSTLANE_B32), DstReg);  in lowerVGPR2SGPRCopies()
1079                             TII->get(AMDGPU::REG_SEQUENCE), DstReg);  in lowerVGPR2SGPRCopies()
1109       Register DstReg = MI.getOperand(0).getReg();  in fixSCCCopies()  local
1121                     TII->get(AMDGPU::COPY), DstReg)  in fixSCCCopies()
1126       if (DstReg == AMDGPU::SCC) {  in fixSCCCopies()