Lines Matching refs:R600InstrInfo
33 R600InstrInfo::R600InstrInfo(const R600Subtarget &ST) in R600InstrInfo() function in R600InstrInfo
36 bool R600InstrInfo::isVector(const MachineInstr &MI) const { in isVector()
40 void R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB, in copyPhysReg()
75 bool R600InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB, in isLegalToSplitMBBAt()
86 bool R600InstrInfo::isMov(unsigned Opcode) const { in isMov()
97 bool R600InstrInfo::isReductionOp(unsigned Opcode) const { in isReductionOp()
101 bool R600InstrInfo::isCubeOp(unsigned Opcode) const { in isCubeOp()
112 bool R600InstrInfo::isALUInstr(unsigned Opcode) const { in isALUInstr()
118 bool R600InstrInfo::hasInstrModifiers(unsigned Opcode) const { in hasInstrModifiers()
126 bool R600InstrInfo::isLDSInstr(unsigned Opcode) const { in isLDSInstr()
134 bool R600InstrInfo::isLDSRetInstr(unsigned Opcode) const { in isLDSRetInstr()
138 bool R600InstrInfo::canBeConsideredALU(const MachineInstr &MI) const { in canBeConsideredALU()
156 bool R600InstrInfo::isTransOnly(unsigned Opcode) const { in isTransOnly()
162 bool R600InstrInfo::isTransOnly(const MachineInstr &MI) const { in isTransOnly()
166 bool R600InstrInfo::isVectorOnly(unsigned Opcode) const { in isVectorOnly()
170 bool R600InstrInfo::isVectorOnly(const MachineInstr &MI) const { in isVectorOnly()
174 bool R600InstrInfo::isExport(unsigned Opcode) const { in isExport()
178 bool R600InstrInfo::usesVertexCache(unsigned Opcode) const { in usesVertexCache()
182 bool R600InstrInfo::usesVertexCache(const MachineInstr &MI) const { in usesVertexCache()
188 bool R600InstrInfo::usesTextureCache(unsigned Opcode) const { in usesTextureCache()
192 bool R600InstrInfo::usesTextureCache(const MachineInstr &MI) const { in usesTextureCache()
199 bool R600InstrInfo::mustBeLastInClause(unsigned Opcode) const { in mustBeLastInClause()
209 bool R600InstrInfo::usesAddressRegister(MachineInstr &MI) const { in usesAddressRegister()
213 bool R600InstrInfo::definesAddressRegister(MachineInstr &MI) const { in definesAddressRegister()
217 bool R600InstrInfo::readsLDSSrcReg(const MachineInstr &MI) const { in readsLDSSrcReg()
233 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const { in getSelIdx()
257 R600InstrInfo::getSrcs(MachineInstr &MI) const { in getSrcs()
317 R600InstrInfo::ExtractSrcs(MachineInstr &MI, in ExtractSrcs()
351 R600InstrInfo::BankSwizzle Swz) { in Swizzle()
355 case R600InstrInfo::ALU_VEC_012_SCL_210: in Swizzle()
357 case R600InstrInfo::ALU_VEC_021_SCL_122: in Swizzle()
360 case R600InstrInfo::ALU_VEC_102_SCL_221: in Swizzle()
363 case R600InstrInfo::ALU_VEC_120_SCL_212: in Swizzle()
367 case R600InstrInfo::ALU_VEC_201: in Swizzle()
371 case R600InstrInfo::ALU_VEC_210: in Swizzle()
378 static unsigned getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) { in getTransSwizzle()
381 case R600InstrInfo::ALU_VEC_012_SCL_210: { in getTransSwizzle()
385 case R600InstrInfo::ALU_VEC_021_SCL_122: { in getTransSwizzle()
389 case R600InstrInfo::ALU_VEC_120_SCL_212: { in getTransSwizzle()
393 case R600InstrInfo::ALU_VEC_102_SCL_221: { in getTransSwizzle()
405 unsigned R600InstrInfo::isLegalUpTo( in isLegalUpTo()
407 const std::vector<R600InstrInfo::BankSwizzle> &Swz, in isLegalUpTo()
409 R600InstrInfo::BankSwizzle TransSwz) const { in isLegalUpTo()
420 if (Swz[i] != R600InstrInfo::ALU_VEC_012_SCL_210 && in isLegalUpTo()
421 Swz[i] != R600InstrInfo::ALU_VEC_021_SCL_122) { in isLegalUpTo()
456 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in NextPossibleSolution()
460 while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210) in NextPossibleSolution()
463 SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210; in NextPossibleSolution()
468 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle; in NextPossibleSolution()
474 bool R600InstrInfo::FindSwizzleForVectorSlot( in FindSwizzleForVectorSlot()
476 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in FindSwizzleForVectorSlot()
478 R600InstrInfo::BankSwizzle TransSwz) const { in FindSwizzleForVectorSlot()
491 isConstCompatible(R600InstrInfo::BankSwizzle TransSwz, in isConstCompatible()
511 R600InstrInfo::fitsReadPortLimitations(const std::vector<MachineInstr *> &IG, in fitsReadPortLimitations()
526 (R600InstrInfo::BankSwizzle)MI->getOperand(Op).getImm()); in fitsReadPortLimitations()
536 static const R600InstrInfo::BankSwizzle TransSwz[] = { in fitsReadPortLimitations()
542 for (R600InstrInfo::BankSwizzle TransBS : TransSwz) { in fitsReadPortLimitations()
557 R600InstrInfo::fitsConstReadLimitations(const std::vector<unsigned> &Consts) in fitsConstReadLimitations()
582 R600InstrInfo::fitsConstReadLimitations(const std::vector<MachineInstr *> &MIs) in fitsConstReadLimitations()
609 R600InstrInfo::CreateTargetScheduleState(const TargetSubtargetInfo &STI) const { in CreateTargetScheduleState()
647 bool R600InstrInfo::analyzeBranch(MachineBasicBlock &MBB, in analyzeBranch()
729 unsigned R600InstrInfo::insertBranch(MachineBasicBlock &MBB, in insertBranch()
776 unsigned R600InstrInfo::removeBranch(MachineBasicBlock &MBB, in removeBranch()
835 bool R600InstrInfo::isPredicated(const MachineInstr &MI) const { in isPredicated()
850 bool R600InstrInfo::isPredicable(const MachineInstr &MI) const { in isPredicable()
873 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB, in isProfitableToIfCvt()
881 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB, in isProfitableToIfCvt()
892 R600InstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB, in isProfitableToDupForIfCvt()
900 R600InstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB, in isProfitableToUnpredicate()
906 R600InstrInfo::reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
939 bool R600InstrInfo::ClobbersPredicate(MachineInstr &MI, in ClobbersPredicate()
945 bool R600InstrInfo::PredicateInstruction(MachineInstr &MI, in PredicateInstruction()
979 unsigned int R600InstrInfo::getPredicationCost(const MachineInstr &) const { in getPredicationCost()
983 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency()
991 unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex, in calculateIndirectAddress()
997 bool R600InstrInfo::expandPostRAPseudo(MachineInstr &MI) const { in expandPostRAPseudo()
1063 void R600InstrInfo::reserveIndirectRegisters(BitVector &Reserved, in reserveIndirectRegisters()
1083 const TargetRegisterClass *R600InstrInfo::getIndirectAddrRegClass() const { in getIndirectAddrRegClass()
1087 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB, in buildIndirectWrite()
1094 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB, in buildIndirectWrite()
1119 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB, in buildIndirectRead()
1126 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB, in buildIndirectRead()
1153 int R600InstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const { in getIndirectIndexBegin()
1185 int R600InstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const { in getIndirectIndexEnd()
1207 unsigned R600InstrInfo::getMaxAlusPerClause() const { in getMaxAlusPerClause()
1211 MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MBB, in buildDefaultInstruction()
1290 MachineInstr *R600InstrInfo::buildSlotOfVectorInstruction( in buildSlotOfVectorInstruction()
1338 MachineInstr *R600InstrInfo::buildMovImm(MachineBasicBlock &BB, in buildMovImm()
1348 MachineInstr *R600InstrInfo::buildMovInstr(MachineBasicBlock *MBB, in buildMovInstr()
1354 int R600InstrInfo::getOperandIdx(const MachineInstr &MI, unsigned Op) const { in getOperandIdx()
1358 int R600InstrInfo::getOperandIdx(unsigned Opcode, unsigned Op) const { in getOperandIdx()
1362 void R600InstrInfo::setImmOperand(MachineInstr &MI, unsigned Op, in setImmOperand()
1374 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr &MI, unsigned SrcIdx, in getFlagOp()
1439 void R600InstrInfo::addFlag(MachineInstr &MI, unsigned Operand, in addFlag()
1460 void R600InstrInfo::clearFlag(MachineInstr &MI, unsigned Operand, in clearFlag()