Lines Matching refs:MVT
33 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass); in R600TargetLowering()
34 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass); in R600TargetLowering()
35 addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass); in R600TargetLowering()
36 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass); in R600TargetLowering()
37 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass); in R600TargetLowering()
38 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass); in R600TargetLowering()
46 setOperationAction(ISD::LOAD, {MVT::i32, MVT::v2i32, MVT::v4i32}, Custom); in R600TargetLowering()
51 for (MVT VT : MVT::integer_valuetypes()) { in R600TargetLowering()
52 setLoadExtAction(Op, VT, MVT::i1, Promote); in R600TargetLowering()
53 setLoadExtAction(Op, VT, MVT::i8, Custom); in R600TargetLowering()
54 setLoadExtAction(Op, VT, MVT::i16, Custom); in R600TargetLowering()
58 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::v2i32, in R600TargetLowering()
59 MVT::v2i1, Expand); in R600TargetLowering()
61 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::v4i32, in R600TargetLowering()
62 MVT::v4i1, Expand); in R600TargetLowering()
64 setOperationAction(ISD::STORE, {MVT::i8, MVT::i32, MVT::v2i32, MVT::v4i32}, in R600TargetLowering()
67 setTruncStoreAction(MVT::i32, MVT::i8, Custom); in R600TargetLowering()
68 setTruncStoreAction(MVT::i32, MVT::i16, Custom); in R600TargetLowering()
71 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom); in R600TargetLowering()
72 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Custom); in R600TargetLowering()
73 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Custom); in R600TargetLowering()
74 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Custom); in R600TargetLowering()
75 setTruncStoreAction(MVT::v32i32, MVT::v32i16, Custom); in R600TargetLowering()
76 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom); in R600TargetLowering()
77 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom); in R600TargetLowering()
78 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Custom); in R600TargetLowering()
79 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Custom); in R600TargetLowering()
80 setTruncStoreAction(MVT::v32i32, MVT::v32i8, Custom); in R600TargetLowering()
83 setTruncStoreAction(MVT::v2i32, MVT::v2i1, Expand); in R600TargetLowering()
84 setTruncStoreAction(MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering()
90 MVT::f32, Expand); in R600TargetLowering()
93 MVT::i32, Expand); in R600TargetLowering()
95 setOperationAction({ISD::FCOS, ISD::FSIN}, MVT::f32, Custom); in R600TargetLowering()
97 setOperationAction(ISD::SETCC, {MVT::v4i32, MVT::v2i32}, Expand); in R600TargetLowering()
99 setOperationAction(ISD::BR_CC, {MVT::i32, MVT::f32}, Expand); in R600TargetLowering()
100 setOperationAction(ISD::BRCOND, MVT::Other, Custom); in R600TargetLowering()
102 setOperationAction(ISD::FSUB, MVT::f32, Expand); in R600TargetLowering()
105 MVT::f64, Custom); in R600TargetLowering()
107 setOperationAction(ISD::SELECT_CC, {MVT::f32, MVT::i32}, Custom); in R600TargetLowering()
109 setOperationAction(ISD::SETCC, {MVT::i32, MVT::f32}, Expand); in R600TargetLowering()
110 setOperationAction({ISD::FP_TO_UINT, ISD::FP_TO_SINT}, {MVT::i1, MVT::i64}, in R600TargetLowering()
113 setOperationAction(ISD::SELECT, {MVT::i32, MVT::f32, MVT::v2i32, MVT::v4i32}, in R600TargetLowering()
119 setOperationAction(ISD::UADDO, MVT::i32, Custom); in R600TargetLowering()
122 setOperationAction(ISD::USUBO, MVT::i32, Custom); in R600TargetLowering()
126 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in R600TargetLowering()
128 setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::v2i1, MVT::v4i1}, Expand); in R600TargetLowering()
131 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in R600TargetLowering()
132 setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::v2i8, MVT::v4i8}, Expand); in R600TargetLowering()
135 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in R600TargetLowering()
136 setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::v2i16, MVT::v4i16}, Expand); in R600TargetLowering()
138 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); in R600TargetLowering()
139 setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::v2i32, MVT::v4i32}, Expand); in R600TargetLowering()
141 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand); in R600TargetLowering()
143 setOperationAction(ISD::FrameIndex, MVT::i32, Custom); in R600TargetLowering()
146 {MVT::v2i32, MVT::v2f32, MVT::v4i32, MVT::v4f32}, Custom); in R600TargetLowering()
149 {MVT::v2i32, MVT::v2f32, MVT::v4i32, MVT::v4f32}, Custom); in R600TargetLowering()
153 setOperationAction({ISD::SHL_PARTS, ISD::SRL_PARTS, ISD::SRA_PARTS}, MVT::i32, in R600TargetLowering()
157 setOperationAction(ISD::FMA, {MVT::f32, MVT::f64}, Expand); in R600TargetLowering()
160 setOperationAction(ISD::FMAD, MVT::f32, Legal); in R600TargetLowering()
164 setOperationAction(ISD::FCOPYSIGN, {MVT::f32, MVT::f64}, Expand); in R600TargetLowering()
167 setOperationAction(ISD::CTPOP, MVT::i32, Expand); in R600TargetLowering()
170 setOperationAction(ISD::CTPOP, MVT::i64, Expand); in R600TargetLowering()
173 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Custom); in R600TargetLowering()
176 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Custom); in R600TargetLowering()
183 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); in R600TargetLowering()
184 setOperationAction(ISD::ADDRSPACECAST, MVT::i32, Custom); in R600TargetLowering()
186 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 }; in R600TargetLowering()
187 for (MVT VT : ScalarIntVTs) in R600TargetLowering()
193 setOperationAction({ISD::ATOMIC_LOAD, ISD::ATOMIC_STORE}, MVT::i32, Expand); in R600TargetLowering()
196 setOperationAction({ISD::INTRINSIC_VOID, ISD::INTRINSIC_WO_CHAIN}, MVT::Other, in R600TargetLowering()
436 DAG.getConstant(0, DL, MVT::i32), // SWZ_X in LowerOperation()
437 DAG.getConstant(1, DL, MVT::i32), // SWZ_Y in LowerOperation()
438 DAG.getConstant(2, DL, MVT::i32), // SWZ_Z in LowerOperation()
439 DAG.getConstant(3, DL, MVT::i32) // SWZ_W in LowerOperation()
470 DAG.getConstant(TextureOp, DL, MVT::i32), in LowerOperation()
472 DAG.getConstant(0, DL, MVT::i32), in LowerOperation()
473 DAG.getConstant(1, DL, MVT::i32), in LowerOperation()
474 DAG.getConstant(2, DL, MVT::i32), in LowerOperation()
475 DAG.getConstant(3, DL, MVT::i32), in LowerOperation()
479 DAG.getConstant(0, DL, MVT::i32), in LowerOperation()
480 DAG.getConstant(1, DL, MVT::i32), in LowerOperation()
481 DAG.getConstant(2, DL, MVT::i32), in LowerOperation()
482 DAG.getConstant(3, DL, MVT::i32), in LowerOperation()
490 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs); in LowerOperation()
494 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
495 DAG.getConstant(0, DL, MVT::i32)), in LowerOperation()
496 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
497 DAG.getConstant(0, DL, MVT::i32)), in LowerOperation()
498 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
499 DAG.getConstant(1, DL, MVT::i32)), in LowerOperation()
500 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
501 DAG.getConstant(1, DL, MVT::i32)), in LowerOperation()
502 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
503 DAG.getConstant(2, DL, MVT::i32)), in LowerOperation()
504 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
505 DAG.getConstant(2, DL, MVT::i32)), in LowerOperation()
506 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
507 DAG.getConstant(3, DL, MVT::i32)), in LowerOperation()
508 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
509 DAG.getConstant(3, DL, MVT::i32)) in LowerOperation()
511 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args); in LowerOperation()
515 MVT PtrVT = getPointerTy(DAG.getDataLayout(), AMDGPUAS::PARAM_I_ADDRESS); in LowerOperation()
587 if (N->getValueType(0) == MVT::i1) { in ReplaceNodeResults()
596 if (N->getValueType(0) == MVT::i1) { in ReplaceNodeResults()
677 MVT ConstPtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS); in LowerGlobalAddress()
694 DAG.getConstantFP(0.15915494309, DL, MVT::f32)), in LowerTrig()
695 DAG.getConstantFP(0.5, DL, MVT::f32))); in LowerTrig()
709 DAG.getConstantFP(-0.5, DL, MVT::f32))); in LowerTrig()
714 DAG.getConstantFP(numbers::pif, DL, MVT::f32)); in LowerTrig()
735 DAG.getValueType(MVT::i1)); in LowerUADDSUBO()
747 MVT::i1, in lowerFP_TO_UINT()
748 Op, DAG.getConstantFP(1.0f, DL, MVT::f32), in lowerFP_TO_UINT()
757 MVT::i1, in lowerFP_TO_SINT()
758 Op, DAG.getConstantFP(-1.0f, DL, MVT::f32), in lowerFP_TO_SINT()
773 DAG.getConstant(ByteOffset, DL, MVT::i32), // PTR in LowerImplicitParameter()
812 if (VT == MVT::f32) { in LowerSELECT_CC()
851 (CompareVT == VT || VT == MVT::i32)) { in LowerSELECT_CC()
921 if (CompareVT == MVT::f32) { in LowerSELECT_CC()
924 } else if (CompareVT == MVT::i32) { in LowerSELECT_CC()
984 DAG.getConstant(SRLPad, DL, MVT::i32)); in stackPtrToRegIndex()
1021 || Store->getValue().getValueType() == MVT::i8); in lowerPrivateTruncStore()
1025 if (Store->getMemoryVT() == MVT::i8) { in lowerPrivateTruncStore()
1027 Mask = DAG.getConstant(0xff, DL, MVT::i32); in lowerPrivateTruncStore()
1028 } else if (Store->getMemoryVT() == MVT::i16) { in lowerPrivateTruncStore()
1030 Mask = DAG.getConstant(0xffff, DL, MVT::i32); in lowerPrivateTruncStore()
1045 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset); in lowerPrivateTruncStore()
1050 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateTruncStore()
1051 DAG.getConstant(0xfffffffc, DL, MVT::i32)); in lowerPrivateTruncStore()
1056 SDValue Dst = DAG.getLoad(MVT::i32, DL, Chain, Ptr, PtrInfo); in lowerPrivateTruncStore()
1061 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateTruncStore()
1062 DAG.getConstant(0x3, DL, MVT::i32)); in lowerPrivateTruncStore()
1065 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateTruncStore()
1066 DAG.getConstant(3, DL, MVT::i32)); in lowerPrivateTruncStore()
1070 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32, in lowerPrivateTruncStore()
1077 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32, in lowerPrivateTruncStore()
1081 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, Mask, ShiftAmt); in lowerPrivateTruncStore()
1085 DstMask = DAG.getNOT(DL, DstMask, MVT::i32); in lowerPrivateTruncStore()
1088 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask); in lowerPrivateTruncStore()
1091 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue); in lowerPrivateTruncStore()
1100 Chain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, NewStore); in lowerPrivateTruncStore()
1128 SDValue NewChain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, Chain); in LowerSTORE()
1155 assert(VT.bitsLE(MVT::i32)); in LowerSTORE()
1157 if (MemVT == MVT::i8) { in LowerSTORE()
1158 MaskConstant = DAG.getConstant(0xFF, DL, MVT::i32); in LowerSTORE()
1160 assert(MemVT == MVT::i16); in LowerSTORE()
1162 MaskConstant = DAG.getConstant(0xFFFF, DL, MVT::i32); in LowerSTORE()
1181 DAG.getConstant(0, DL, MVT::i32), in LowerSTORE()
1182 DAG.getConstant(0, DL, MVT::i32), in LowerSTORE()
1185 SDValue Input = DAG.getBuildVector(MVT::v4i32, DL, Src); in LowerSTORE()
1190 } else if (Ptr->getOpcode() != AMDGPUISD::DWORDADDR && VT.bitsGE(MVT::i32)) { in LowerSTORE()
1207 if (MemVT.bitsLT(MVT::i32)) in LowerSTORE()
1276 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset); in lowerPrivateExtLoad()
1281 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateExtLoad()
1282 DAG.getConstant(0xfffffffc, DL, MVT::i32)); in lowerPrivateExtLoad()
1287 SDValue Read = DAG.getLoad(MVT::i32, DL, Chain, Ptr, PtrInfo); in lowerPrivateExtLoad()
1290 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, in lowerPrivateExtLoad()
1291 LoadPtr, DAG.getConstant(0x3, DL, MVT::i32)); in lowerPrivateExtLoad()
1294 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateExtLoad()
1295 DAG.getConstant(3, DL, MVT::i32)); in lowerPrivateExtLoad()
1298 SDValue Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Read, ShiftAmt); in lowerPrivateExtLoad()
1305 Ret = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode); in lowerPrivateExtLoad()
1325 ExtType != ISD::NON_EXTLOAD && MemVT.bitsLT(MVT::i32)) { in LowerLOAD()
1354 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32, in LowerLOAD()
1355 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, in LowerLOAD()
1356 DAG.getConstant(4, DL, MVT::i32)), in LowerLOAD()
1358 AMDGPUAS::CONSTANT_BUFFER_0, DL, MVT::i32) in LowerLOAD()
1363 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in LowerLOAD()
1364 DAG.getConstant(0, DL, MVT::i32)); in LowerLOAD()
1382 assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8)); in LowerLOAD()
1399 assert(VT == MVT::i32); in LowerLOAD()
1400 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(2, DL, MVT::i32)); in LowerLOAD()
1401 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, MVT::i32, Ptr); in LowerLOAD()
1402 return DAG.getLoad(MVT::i32, DL, Chain, Ptr, LoadNode->getMemOperand()); in LowerLOAD()
1515 DAG.getConstant(PartOffset, DL, MVT::i32), DAG.getUNDEF(MVT::i32), in LowerFormalArguments()
1529 return MVT::i32; in getSetCCResultType()
1548 if (!VT.isSimple() || VT == MVT::Other) in allowsMisalignedMemoryAccesses()
1551 if (VT.bitsLT(MVT::i32)) in allowsMisalignedMemoryAccesses()
1558 return VT.bitsGT(MVT::i32) && Alignment >= Align(4); in allowsMisalignedMemoryAccesses()
1583 NewBldVec[i] = DAG.getUNDEF(MVT::f32); in CompactSwizzlableVector()
1586 NewBldVec[i] = DAG.getUNDEF(MVT::f32); in CompactSwizzlableVector()
1654 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32); in OptimizeSwizzle()
1662 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32); in OptimizeSwizzle()
1677 if (LoadNode->getMemoryVT().getScalarType() != MVT::i32 || !ISD::isNON_EXTLoad(LoadNode)) in constBufferLoad()
1693 DAG.getConstant(4 * i + ConstantBlock * 16, DL, MVT::i32)); in constBufferLoad()
1694 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr); in constBufferLoad()
1696 EVT NewVT = MVT::v4i32; in constBufferLoad()
1704 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in constBufferLoad()
1705 DAG.getConstant(0, DL, MVT::i32)); in constBufferLoad()
1727 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) { in PerformDAGCombine()
1746 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS in PerformDAGCombine()
1747 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True in PerformDAGCombine()
1756 DAG.getConstant(-1, DL, MVT::i32), // True in PerformDAGCombine()
1757 DAG.getConstant(0, DL, MVT::i32), // False in PerformDAGCombine()
1958 Neg = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32); in FoldOperand()
1964 Abs = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32); in FoldOperand()
2015 Src = DAG.getRegister(R600::ALU_CONST, MVT::f32); in FoldOperand()
2023 Src = DAG.getRegister(R600::ALU_LITERAL_X, MVT::i32); in FoldOperand()
2062 Imm = DAG.getTargetConstant(ImmValue, SDLoc(ParentNode), MVT::i32); in FoldOperand()
2064 Src = DAG.getRegister(ImmReg, MVT::i32); in FoldOperand()