Lines Matching refs:STI
44 StringRef Annot, const MCSubtargetInfo &STI, in printInst() argument
47 printInstruction(MI, Address, STI, OS); in printInst()
52 const MCSubtargetInfo &STI, in printU4ImmOperand() argument
58 const MCSubtargetInfo &STI, in printU16ImmOperand() argument
66 printU32ImmOperand(MI, OpNo, STI, O); in printU16ImmOperand()
85 const MCSubtargetInfo &STI, in printU32ImmOperand() argument
98 const MCSubtargetInfo &STI, in printOffset() argument
107 if (AMDGPU::isGFX12(STI) && IsVBuffer) in printOffset()
115 const MCSubtargetInfo &STI, in printFlatOffset() argument
124 AMDGPU::isGFX12(STI); in printFlatOffset()
127 O << formatDec(SignExtend32(Imm, AMDGPU::getNumFlatOffsetBits(STI))); in printFlatOffset()
134 const MCSubtargetInfo &STI, in printOffset0() argument
143 const MCSubtargetInfo &STI, in printOffset1() argument
152 const MCSubtargetInfo &STI, in printSMRDOffset8() argument
154 printU32ImmOperand(MI, OpNo, STI, O); in printSMRDOffset8()
158 const MCSubtargetInfo &STI, in printSMEMOffset() argument
164 const MCSubtargetInfo &STI, in printSMEMOffsetMod() argument
167 printSMEMOffset(MI, OpNo, STI, O); in printSMEMOffsetMod()
171 const MCSubtargetInfo &STI, in printSMRDLiteralOffset() argument
173 printU32ImmOperand(MI, OpNo, STI, O); in printSMRDLiteralOffset()
177 const MCSubtargetInfo &STI, raw_ostream &O) { in printCPol() argument
180 if (AMDGPU::isGFX12Plus(STI)) { in printCPol()
191 O << ((AMDGPU::isGFX940(STI) && in printCPol()
195 O << (AMDGPU::isGFX940(STI) ? " nt" : " slc"); in printCPol()
196 if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI)) in printCPol()
198 if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI)) in printCPol()
199 O << (AMDGPU::isGFX940(STI) ? " sc1" : " scc"); in printCPol()
288 const MCSubtargetInfo &STI, raw_ostream &O) { in printDMask() argument
291 printU16ImmOperand(MI, OpNo, STI, O); in printDMask()
296 const MCSubtargetInfo &STI, raw_ostream &O) { in printDim() argument
308 const MCSubtargetInfo &STI, raw_ostream &O) { in printR128A16() argument
309 if (STI.hasFeature(AMDGPU::FeatureR128A16)) in printR128A16()
316 const MCSubtargetInfo &STI, in printFORMAT() argument
321 const MCSubtargetInfo &STI, in printSymbolicFormat() argument
330 if (AMDGPU::isGFX10Plus(STI)) { in printSymbolicFormat()
333 if (isValidUnifiedFormat(Val, STI)) { in printSymbolicFormat()
334 O << " format:[" << getUnifiedFormatName(Val, STI) << ']'; in printSymbolicFormat()
341 if (isValidDfmtNfmt(Val, STI)) { in printSymbolicFormat()
353 O << getNfmtName(Nfmt, STI); in printSymbolicFormat()
381 const MCSubtargetInfo &STI, raw_ostream &O) { in printVOPDst() argument
400 printRegularOperand(MI, OpNo, STI, O); in printVOPDst()
436 printDefaultVccOperand(false, STI, O); in printVOPDst()
442 const MCSubtargetInfo &STI, raw_ostream &O) { in printVINTRPDst() argument
443 if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI)) in printVINTRPDst()
448 printRegularOperand(MI, OpNo, STI, O); in printVINTRPDst()
452 const MCSubtargetInfo &STI, in printImmediateInt16() argument
465 static bool printImmediateFloat16(uint32_t Imm, const MCSubtargetInfo &STI, in printImmediateFloat16() argument
483 else if (Imm == 0x3118 && STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm)) in printImmediateFloat16()
492 const MCSubtargetInfo &STI, in printImmediate16() argument
501 if (printImmediateFloat16(HImm, STI, O)) in printImmediate16()
509 const MCSubtargetInfo &STI, in printImmediateV216() argument
521 if (printImmediateFloat32(Imm, STI, O)) in printImmediateV216()
528 printImmediateFloat16(static_cast<uint16_t>(Imm), STI, O)) in printImmediateV216()
539 const MCSubtargetInfo &STI, in printImmediateFloat32() argument
560 STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm)) in printImmediateFloat32()
569 const MCSubtargetInfo &STI, in printImmediate32() argument
577 if (printImmediateFloat32(Imm, STI, O)) in printImmediate32()
584 const MCSubtargetInfo &STI, in printImmediate64() argument
611 STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm)) in printImmediate64()
626 const MCSubtargetInfo &STI, in printBLGP() argument
632 if (AMDGPU::isGFX940(STI)) { in printBLGP()
648 const MCSubtargetInfo &STI, in printCBSZ() argument
658 const MCSubtargetInfo &STI, in printABID() argument
668 const MCSubtargetInfo &STI, in printDefaultVccOperand() argument
672 printRegOperand(STI.hasFeature(AMDGPU::FeatureWavefrontSize64) in printDefaultVccOperand()
681 const MCSubtargetInfo &STI, in printWaitVDST() argument
688 const MCSubtargetInfo &STI, in printWaitVAVDst() argument
695 const MCSubtargetInfo &STI, in printWaitVMVSrc() argument
702 const MCSubtargetInfo &STI, in printWaitEXP() argument
718 const MCSubtargetInfo &STI, in printOperand() argument
731 printDefaultVccOperand(true, STI, O); in printOperand()
733 printRegularOperand(MI, OpNo, STI, O); in printOperand()
738 const MCSubtargetInfo &STI, in printRegularOperand() argument
779 printImmediate32(Op.getImm(), STI, O); in printRegularOperand()
783 printImmediate64(Op.getImm(), STI, O, false); in printRegularOperand()
788 printImmediate64(Op.getImm(), STI, O, true); in printRegularOperand()
793 printImmediateInt16(Op.getImm(), STI, O); in printRegularOperand()
799 printImmediate16(Op.getImm(), STI, O); in printRegularOperand()
807 printImmediateV216(Op.getImm(), OpTy, STI, O); in printRegularOperand()
816 printImmediate32(Op.getImm(), STI, O); in printRegularOperand()
834 printImmediate32(llvm::bit_cast<uint32_t>((float)Value), STI, O); in printRegularOperand()
836 printImmediate64(llvm::bit_cast<uint64_t>(Value), STI, O, true); in printRegularOperand()
890 printDefaultVccOperand(OpNo == 0, STI, O); in printRegularOperand()
899 printSymbolicFormat(MI, STI, O); in printRegularOperand()
905 const MCSubtargetInfo &STI, in printOperandAndFPInputMods() argument
909 printDefaultVccOperand(true, STI, O); in printOperandAndFPInputMods()
933 printRegularOperand(MI, OpNo + 1, STI, O); in printOperandAndFPInputMods()
951 printDefaultVccOperand(OpNo == 0, STI, O); in printOperandAndFPInputMods()
958 const MCSubtargetInfo &STI, in printOperandAndIntInputMods() argument
962 printDefaultVccOperand(true, STI, O); in printOperandAndIntInputMods()
967 printRegularOperand(MI, OpNo + 1, STI, O); in printOperandAndIntInputMods()
980 printDefaultVccOperand(OpNo == 0, STI, O); in printOperandAndIntInputMods()
986 const MCSubtargetInfo &STI, in printDPP8() argument
988 if (!AMDGPU::isGFX10Plus(STI)) in printDPP8()
1000 const MCSubtargetInfo &STI, in printDPPCtrl() argument
1029 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1035 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1041 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1047 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1057 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1063 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1070 if (AMDGPU::isGFX90A(STI)) { in printDPPCtrl()
1072 } else if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1082 if (!AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1094 const MCSubtargetInfo &STI, in printDppRowMask() argument
1097 printU4ImmOperand(MI, OpNo, STI, O); in printDppRowMask()
1101 const MCSubtargetInfo &STI, in printDppBankMask() argument
1104 printU4ImmOperand(MI, OpNo, STI, O); in printDppBankMask()
1108 const MCSubtargetInfo &STI, in printDppBoundCtrl() argument
1117 const MCSubtargetInfo &STI, raw_ostream &O) { in printDppFI() argument
1143 const MCSubtargetInfo &STI, in printSDWADstSel() argument
1150 const MCSubtargetInfo &STI, in printSDWASrc0Sel() argument
1157 const MCSubtargetInfo &STI, in printSDWASrc1Sel() argument
1164 const MCSubtargetInfo &STI, in printSDWADstUnused() argument
1179 const MCSubtargetInfo &STI, raw_ostream &O, in printExpSrcN() argument
1198 const MCSubtargetInfo &STI, in printExpSrc0() argument
1200 printExpSrcN(MI, OpNo, STI, O, 0); in printExpSrc0()
1204 const MCSubtargetInfo &STI, in printExpSrc1() argument
1206 printExpSrcN(MI, OpNo, STI, O, 1); in printExpSrc1()
1210 const MCSubtargetInfo &STI, in printExpSrc2() argument
1212 printExpSrcN(MI, OpNo, STI, O, 2); in printExpSrc2()
1216 const MCSubtargetInfo &STI, in printExpSrc3() argument
1218 printExpSrcN(MI, OpNo, STI, O, 3); in printExpSrc3()
1222 const MCSubtargetInfo &STI, in printExpTgt() argument
1231 if (getTgtName(Id, TgtName, Index) && isSupportedTgtId(Id, STI)) { in printExpTgt()
1322 const MCSubtargetInfo &STI, in printOpSel() argument
1349 const MCSubtargetInfo &STI, in printOpSelHi() argument
1355 const MCSubtargetInfo &STI, in printNegLo() argument
1361 const MCSubtargetInfo &STI, in printNegHi() argument
1367 const MCSubtargetInfo &STI, in printIndexKey8bit() argument
1377 const MCSubtargetInfo &STI, in printIndexKey16bit() argument
1387 const MCSubtargetInfo &STI, in printInterpSlot() argument
1406 const MCSubtargetInfo &STI, in printInterpAttr() argument
1413 const MCSubtargetInfo &STI, in printInterpAttrChan() argument
1420 const MCSubtargetInfo &STI, in printGPRIdxMode() argument
1443 const MCSubtargetInfo &STI, in printMemOperand() argument
1445 printRegularOperand(MI, OpNo, STI, O); in printMemOperand()
1447 printRegularOperand(MI, OpNo + 1, STI, O); in printMemOperand()
1471 const MCSubtargetInfo &STI, in printOModSI() argument
1483 const MCSubtargetInfo &STI, in printSendMsg() argument
1492 decodeMsg(Imm16, MsgId, OpId, StreamId, STI); in printSendMsg()
1494 StringRef MsgName = getMsgName(MsgId, STI); in printSendMsg()
1496 if (!MsgName.empty() && isValidMsgOp(MsgId, OpId, STI) && in printSendMsg()
1497 isValidMsgStream(MsgId, OpId, StreamId, STI)) { in printSendMsg()
1499 if (msgRequiresOp(MsgId, STI)) { in printSendMsg()
1500 O << ", " << getMsgOpName(MsgId, OpId, STI); in printSendMsg()
1501 if (msgSupportsStream(MsgId, OpId, STI)) { in printSendMsg()
1547 const MCSubtargetInfo &STI, in printSwizzle() argument
1617 const MCSubtargetInfo &STI, in printSWaitCnt() argument
1619 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU()); in printSWaitCnt()
1652 const MCSubtargetInfo &STI, in printDepCtr() argument
1659 if (isSymbolicDepCtrEncoding(Imm16, HasNonDefaultVal, STI)) { in printDepCtr()
1665 while (decodeDepCtr(Imm16, Id, Name, Val, IsDefault, STI)) { in printDepCtr()
1679 const MCSubtargetInfo &STI, in printSDelayALU() argument
1722 const MCSubtargetInfo &STI, raw_ostream &O) { in printHwreg() argument
1730 StringRef HwRegName = getHwreg(Id, STI); in printHwreg()
1745 const MCSubtargetInfo &STI, in printEndpgm() argument