Lines Matching refs:MCID
250 const MCInstrDesc &MCID = MCII.get(Opcode); in generateWaitCntInfo() local
251 if ((MCID.TSFlags & SIInstrFlags::DS) && in generateWaitCntInfo()
252 (MCID.TSFlags & SIInstrFlags::LGKM_CNT)) { in generateWaitCntInfo()
256 } else if (MCID.TSFlags & SIInstrFlags::FLAT) { in generateWaitCntInfo()
264 else if (MCID.mayLoad() && !(MCID.TSFlags & SIInstrFlags::IsAtomicNoRet)) in generateWaitCntInfo()
268 } else if (isVMEM(MCID) && !AMDGPU::getMUBUFIsBufferInv(Opcode)) { in generateWaitCntInfo()
271 else if ((MCID.mayLoad() && in generateWaitCntInfo()
272 !(MCID.TSFlags & SIInstrFlags::IsAtomicNoRet)) || in generateWaitCntInfo()
273 ((MCID.TSFlags & SIInstrFlags::MIMG) && !MCID.mayLoad() && in generateWaitCntInfo()
274 !MCID.mayStore())) in generateWaitCntInfo()
276 else if (MCID.mayStore()) in generateWaitCntInfo()
284 (MCID.mayStore() || (MCID.TSFlags & SIInstrFlags::IsAtomicRet))) in generateWaitCntInfo()
286 } else if (MCID.TSFlags & SIInstrFlags::SMRD) { in generateWaitCntInfo()
288 } else if (MCID.TSFlags & SIInstrFlags::EXP) { in generateWaitCntInfo()
304 bool AMDGPUCustomBehaviour::isVMEM(const MCInstrDesc &MCID) { in isVMEM() argument
305 return MCID.TSFlags & SIInstrFlags::MUBUF || in isVMEM()
306 MCID.TSFlags & SIInstrFlags::MTBUF || in isVMEM()
307 MCID.TSFlags & SIInstrFlags::MIMG; in isVMEM()
326 const MCInstrDesc &MCID = MCII.get(Opcode); in isGWS() local
327 return MCID.TSFlags & SIInstrFlags::GWS; in isGWS()