39                                    const MachineInstr &SecondMI) {  in checkVOPDRegConstraints()  argument
59       if (&*MII == &SecondMI)  in checkVOPDRegConstraints()
65   for (const auto &Use : SecondMI.uses())  in checkVOPDRegConstraints()
70     const MachineInstr &MI = (OpcodeIdx == VOPD::X) ? FirstMI : SecondMI;  in checkVOPDRegConstraints()
78       AMDGPU::getVOPDInstInfo(FirstMI.getDesc(), SecondMI.getDesc());  in checkVOPDRegConstraints()
81     const MachineInstr &MI = (CompIdx == VOPD::X) ? FirstMI : SecondMI;  in checkVOPDRegConstraints()
110                  SecondMI.getOpcode() == AMDGPU::V_MOV_B32_e32;  in checkVOPDRegConstraints()
116                     << "\n\tY: " << SecondMI << "\n");  in checkVOPDRegConstraints()
126                                        const MachineInstr &SecondMI) {  in shouldScheduleVOPDAdjacent()  argument
128   unsigned Opc2 = SecondMI.getOpcode();  in shouldScheduleVOPDAdjacent()
142   return checkVOPDRegConstraints(STII, *FirstMI, SecondMI);  in shouldScheduleVOPDAdjacent()