38                                    const MachineInstr &FirstMI,  in checkVOPDRegConstraints()  argument
42   const MachineFunction *MF = FirstMI.getMF();  in checkVOPDRegConstraints()
57     for (auto MII = MachineBasicBlock::const_iterator(&FirstMI);  in checkVOPDRegConstraints()
58          MII != FirstMI.getParent()->instr_end(); ++MII) {  in checkVOPDRegConstraints()
66     if (Use.isReg() && FirstMI.modifiesRegister(Use.getReg(), TRI))  in checkVOPDRegConstraints()
70     const MachineInstr &MI = (OpcodeIdx == VOPD::X) ? FirstMI : SecondMI;  in checkVOPDRegConstraints()
78       AMDGPU::getVOPDInstInfo(FirstMI.getDesc(), SecondMI.getDesc());  in checkVOPDRegConstraints()
81     const MachineInstr &MI = (CompIdx == VOPD::X) ? FirstMI : SecondMI;  in checkVOPDRegConstraints()
109                  FirstMI.getOpcode() == AMDGPU::V_MOV_B32_e32 &&  in checkVOPDRegConstraints()
115   LLVM_DEBUG(dbgs() << "VOPD Reg Constraints Passed\n\tX: " << FirstMI  in checkVOPDRegConstraints()
125                                        const MachineInstr *FirstMI,  in shouldScheduleVOPDAdjacent()  argument
132   if (!FirstMI)  in shouldScheduleVOPDAdjacent()
135   unsigned Opc = FirstMI->getOpcode();  in shouldScheduleVOPDAdjacent()
142   return checkVOPDRegConstraints(STII, *FirstMI, SecondMI);  in shouldScheduleVOPDAdjacent()