178   const MachineOperand *RegOp = TII->getNamedOperand(RegInstr,  in getHWReg()
831         TII->getNamedOperand(MI, AMDGPU::OpName::soffset);  in createsVALUHazard()
895       Register Def = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)->getReg();  in checkVALUHazards()
919         if (auto *DstSel = TII->getNamedOperand(MI, AMDGPU::OpName::dst_sel))  in checkVALUHazards()
924             !(TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers)  in checkVALUHazards()
930       if (auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)) {  in checkVALUHazards()
987       MachineOperand *Src = TII.getNamedOperand(*VALU, AMDGPU::OpName::src0);  in checkVALUHazards()
1054       TII->getNamedOperand(*RWLane, AMDGPU::OpName::src1);  in checkRWLaneHazards()
1133   auto *Src0 = TII->getNamedOperand(*MI, AMDGPU::OpName::src0);  in fixVcmpxPermlaneHazards()
1213   const MachineOperand *SDST = TII->getNamedOperand(*MI, SDSTName);  in fixSMEMtoVectorWriteHazards()
1299       if (TII->getNamedOperand(MI, AMDGPU::OpName::sdst))  in fixVcmpxExecWARHazard()
1410   const MachineOperand *VDST = TII.getNamedOperand(*MI, AMDGPU::OpName::vdst);  in fixLdsDirectVALUHazard()
1443       TII.getNamedOperand(*MI, AMDGPU::OpName::waitvdst);  in fixLdsDirectVALUHazard()
1453   const MachineOperand *VDST = TII.getNamedOperand(*MI, AMDGPU::OpName::vdst);  in fixLdsDirectVMEMHazard()
1471             !TII.getNamedOperand(I, AMDGPU::OpName::waitvsrc)->getImm());  in fixLdsDirectVMEMHazard()
1479     TII.getNamedOperand(*MI, AMDGPU::OpName::waitvsrc)->setImm(0);  in fixLdsDirectVMEMHazard()
1732         TII->getNamedOperand(*MI, AMDGPU::OpName::src0)->getReg();  in fixWMMAHazards()
1734         TII->getNamedOperand(*MI, AMDGPU::OpName::src1)->getReg();  in fixWMMAHazards()
1737         TII->getNamedOperand(I, AMDGPU::OpName::vdst)->getReg();  in fixWMMAHazards()
1747         TII->getNamedOperand(*MI, AMDGPU::OpName::src2);  in fixWMMAHazards()
1754           TII->getNamedOperand(*MI, AMDGPU::OpName::src2_modifiers);  in fixWMMAHazards()
1769             TII->getNamedOperand(*MI, AMDGPU::OpName::src2)->getReg();  in fixWMMAHazards()
1806   MachineOperand *Amt = TII.getNamedOperand(*MI, AMDGPU::OpName::src0);  in fixShift64HighRegBug()
1819   MachineOperand *Src1 = TII.getNamedOperand(*MI, AMDGPU::OpName::src1);  in fixShift64HighRegBug()
1905   const auto *Offset = TII->getNamedOperand(*MI, AMDGPU::OpName::offset);  in checkNSAtoVMEMHazard()
2131       Register Reg = TII.getNamedOperand(MI, AMDGPU::OpName::src2)->getReg();  in checkMAIHazards908()
2690           TII.getNamedOperand(MI, AMDGPU::OpName::src2);  in checkMAIVALUHazards()
2766   const MachineOperand *SDSTOp = TII.getNamedOperand(*MI, AMDGPU::OpName::sdst);  in fixVALUMaskWriteHazard()
2806       const MachineOperand *SSRCOp = TII.getNamedOperand(I, AMDGPU::OpName::src2);  in fixVALUMaskWriteHazard()