234   auto DPPInst = BuildMI(*OrigMI.getParent(), OrigMI,  in createDPPInst()  local
242       DPPInst.add(*Dst);  in createDPPInst()
246       if (TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, SDst)) {  in createDPPInst()
247         DPPInst.add(*SDst);  in createDPPInst()
262       DPPInst.addReg(CombOldVGPR.Reg, Def ? 0 : RegState::Undef,  in createDPPInst()
283       DPPInst.addImm(Mod0->getImm());  in createDPPInst()
286       DPPInst.addImm(0);  in createDPPInst()
292     if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) {  in createDPPInst()
297     DPPInst.add(*Src0);  in createDPPInst()
298     DPPInst->getOperand(NumOperands).setIsKill(false);  in createDPPInst()
307       DPPInst.addImm(Mod1->getImm());  in createDPPInst()
310       DPPInst.addImm(0);  in createDPPInst()
320         assert(getOperandSize(*DPPInst, Src0Idx, *MRI) ==  in createDPPInst()
321                    getOperandSize(*DPPInst, NumOperands, *MRI) &&  in createDPPInst()
325       if (!TII->isOperandLegal(*DPPInst.getInstr(), OpNum, Src1)) {  in createDPPInst()
330       DPPInst.add(*Src1);  in createDPPInst()
340       DPPInst.addImm(Mod2->getImm());  in createDPPInst()
345       if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) ||  in createDPPInst()
346           !TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) {  in createDPPInst()
351       DPPInst.add(*Src2);  in createDPPInst()
358         DPPInst.addImm(ClampOpr->getImm());  in createDPPInst()
363         DPPInst.add(*VdstInOpr);  in createDPPInst()
367         DPPInst.addImm(OmodOpr->getImm());  in createDPPInst()
386           DPPInst.addImm(OpSel);  in createDPPInst()
404           DPPInst.addImm(OpSelHi);  in createDPPInst()
408         DPPInst.addImm(NegOpr->getImm());  in createDPPInst()
412         DPPInst.addImm(NegHiOpr->getImm());  in createDPPInst()
415     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl));  in createDPPInst()
416     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask));  in createDPPInst()
417     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask));  in createDPPInst()
418     DPPInst.addImm(CombBCZ ? 1 : 0);  in createDPPInst()
422     DPPInst.getInstr()->eraseFromParent();  in createDPPInst()
425   LLVM_DEBUG(dbgs() << "  combined:  " << *DPPInst.getInstr());  in createDPPInst()
426   return DPPInst.getInstr();  in createDPPInst()
702       if (auto *DPPInst = createDPPInst(OrigMI, MovMI, CombOldVGPR,  in combineDPPMov()  local
704         DPPMIs.push_back(DPPInst);  in combineDPPMov()
714         if (auto *DPPInst =  in combineDPPMov()  local
717           DPPMIs.push_back(DPPInst);  in combineDPPMov()