64                               RegSubRegPair CombOldVGPR,
69                               RegSubRegPair CombOldVGPR, bool CombBCZ,
206                                            RegSubRegPair CombOldVGPR,  in createDPPInst()  argument
257           CombOldVGPR,  in createDPPInst()
261       auto *Def = getVRegSubRegDef(CombOldVGPR, *MRI);  in createDPPInst()
262       DPPInst.addReg(CombOldVGPR.Reg, Def ? 0 : RegState::Undef,  in createDPPInst()
263                      CombOldVGPR.SubReg);  in createDPPInst()
482     MachineInstr &OrigMI, MachineInstr &MovMI, RegSubRegPair CombOldVGPR,  in createDPPInst()  argument
484   assert(CombOldVGPR.Reg);  in createDPPInst()
495     CombOldVGPR = getRegSubRegPair(*Src1);  in createDPPInst()
498     if (!isOfRegClass(CombOldVGPR, *RC, *MRI)) {  in createDPPInst()
503   return createDPPInst(OrigMI, MovMI, CombOldVGPR, CombBCZ, IsShrinkable);  in createDPPInst()
608   auto CombOldVGPR = getRegSubRegPair(*OldOpnd);  in combineDPPMov()  local
612     CombOldVGPR = RegSubRegPair(  in combineDPPMov()
615                              TII->get(AMDGPU::IMPLICIT_DEF), CombOldVGPR.Reg);  in combineDPPMov()
702       if (auto *DPPInst = createDPPInst(OrigMI, MovMI, CombOldVGPR,  in combineDPPMov()
715                 createDPPInst(*NewMI, MovMI, CombOldVGPR, OldOpndValue, CombBCZ,  in combineDPPMov()