134         Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm));      \
792                     createRegOperand(VAddrRCID, Bytes[i]));  in getInstruction()
880       insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC),  in convertSDWAInst()
1265 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {  in createRegOperand()  function in AMDGPUDisassembler
1270 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,  in createRegOperand()  function in AMDGPUDisassembler
1276   return createRegOperand(RegCl.getRegister(Val));  in createRegOperand()
1326   return createRegOperand(SRegClassID, Val >> shift);  in createSRegOperand()
1332   return createRegOperand(AMDGPU::VGPR_16RegClassID, RegIdxInVGPR16);  in createVGPR16Operand()
1590     return createRegOperand(IsAGPR ? getAgprClassId(Width)  in decodeSrcOp()
1656   return createRegOperand(getVgprClassId(Width), Val);  in decodeVOPDDstYOp()
1664   case 102: return createRegOperand(FLAT_SCR_LO);  in decodeSpecialReg32()
1665   case 103: return createRegOperand(FLAT_SCR_HI);  in decodeSpecialReg32()
1666   case 104: return createRegOperand(XNACK_MASK_LO);  in decodeSpecialReg32()
1667   case 105: return createRegOperand(XNACK_MASK_HI);  in decodeSpecialReg32()
1668   case 106: return createRegOperand(VCC_LO);  in decodeSpecialReg32()
1669   case 107: return createRegOperand(VCC_HI);  in decodeSpecialReg32()
1670   case 108: return createRegOperand(TBA_LO);  in decodeSpecialReg32()
1671   case 109: return createRegOperand(TBA_HI);  in decodeSpecialReg32()
1672   case 110: return createRegOperand(TMA_LO);  in decodeSpecialReg32()
1673   case 111: return createRegOperand(TMA_HI);  in decodeSpecialReg32()
1675     return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0);  in decodeSpecialReg32()
1677     return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL);  in decodeSpecialReg32()
1678   case 126: return createRegOperand(EXEC_LO);  in decodeSpecialReg32()
1679   case 127: return createRegOperand(EXEC_HI);  in decodeSpecialReg32()
1680   case 235: return createRegOperand(SRC_SHARED_BASE_LO);  in decodeSpecialReg32()
1681   case 236: return createRegOperand(SRC_SHARED_LIMIT_LO);  in decodeSpecialReg32()
1682   case 237: return createRegOperand(SRC_PRIVATE_BASE_LO);  in decodeSpecialReg32()
1683   case 238: return createRegOperand(SRC_PRIVATE_LIMIT_LO);  in decodeSpecialReg32()
1684   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);  in decodeSpecialReg32()
1685   case 251: return createRegOperand(SRC_VCCZ);  in decodeSpecialReg32()
1686   case 252: return createRegOperand(SRC_EXECZ);  in decodeSpecialReg32()
1687   case 253: return createRegOperand(SRC_SCC);  in decodeSpecialReg32()
1688   case 254: return createRegOperand(LDS_DIRECT);  in decodeSpecialReg32()
1699   case 102: return createRegOperand(FLAT_SCR);  in decodeSpecialReg64()
1700   case 104: return createRegOperand(XNACK_MASK);  in decodeSpecialReg64()
1701   case 106: return createRegOperand(VCC);  in decodeSpecialReg64()
1702   case 108: return createRegOperand(TBA);  in decodeSpecialReg64()
1703   case 110: return createRegOperand(TMA);  in decodeSpecialReg64()
1706       return createRegOperand(SGPR_NULL);  in decodeSpecialReg64()
1710       return createRegOperand(SGPR_NULL);  in decodeSpecialReg64()
1712   case 126: return createRegOperand(EXEC);  in decodeSpecialReg64()
1713   case 235: return createRegOperand(SRC_SHARED_BASE);  in decodeSpecialReg64()
1714   case 236: return createRegOperand(SRC_SHARED_LIMIT);  in decodeSpecialReg64()
1715   case 237: return createRegOperand(SRC_PRIVATE_BASE);  in decodeSpecialReg64()
1716   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);  in decodeSpecialReg64()
1717   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);  in decodeSpecialReg64()
1718   case 251: return createRegOperand(SRC_VCCZ);  in decodeSpecialReg64()
1719   case 252: return createRegOperand(SRC_EXECZ);  in decodeSpecialReg64()
1720   case 253: return createRegOperand(SRC_SCC);  in decodeSpecialReg64()
1738       return createRegOperand(getVgprClassId(Width),  in decodeSDWASrc()
1763     return createRegOperand(getVgprClassId(Width), Val);  in decodeSDWASrc()
1799     return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);  in decodeSDWAVopcDst()