138                      ImmWidth)                                                 \  argument
145                                         MandatoryLiteral, ImmWidth));          \
181 #define DECODE_OPERAND_SRC_REG_OR_IMM_9(RegClass, OpWidth, ImmWidth)           \  argument
182   DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, Imm,      \
183                false, ImmWidth)
185 #define DECODE_OPERAND_SRC_REG_OR_IMM_9_TYPED(Name, OpWidth, ImmWidth)         \  argument
186   DECODE_SrcOp(decodeOperand_##Name, 9, OpWidth, Imm, false, ImmWidth)
190 #define DECODE_OPERAND_SRC_REG_OR_IMM_A9(RegClass, OpWidth, ImmWidth)          \  argument
191   DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth,           \
192                Imm | 512, false, ImmWidth)
194 #define DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(RegClass, OpWidth, ImmWidth)  \  argument
195   DECODE_SrcOp(decodeOperand_##RegClass##_Deferred##_Imm##ImmWidth, 9,         \
196                OpWidth, Imm, true, ImmWidth)
1452 MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm) {  in decodeFPImmed()  argument
1460   switch (ImmWidth) {  in decodeFPImmed()
1581                                           unsigned ImmWidth, bool IsFP) const {  in decodeSrcOp()  argument
1593   return decodeNonVGPRSrcOp(Width, Val & 0xFF, MandatoryLiteral, ImmWidth,  in decodeSrcOp()
1600                                                  unsigned ImmWidth,  in decodeNonVGPRSrcOp()  argument
1622     return decodeFPImmed(ImmWidth, Val);  in decodeNonVGPRSrcOp()
1629       return decodeLiteralConstant(IsFP && ImmWidth == 64);  in decodeNonVGPRSrcOp()
1728                                             unsigned ImmWidth) const {  in decodeSDWASrc()
1759       return decodeFPImmed(ImmWidth, SVal);  in decodeSDWASrc()