75 static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm,  in decodeSOPPBrTarget()  argument
82   APInt SignedOffset(18, Imm * 4, true);  in decodeSOPPBrTarget()
87   return addOperand(Inst, MCOperand::createImm(Imm));  in decodeSOPPBrTarget()
90 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr,  in decodeSMEMOffset()  argument
95     Offset = SignExtend64<24>(Imm);  in decodeSMEMOffset()
97     Offset = Imm & 0xFFFFF;  in decodeSMEMOffset()
99     Offset = SignExtend64<21>(Imm);  in decodeSMEMOffset()
118   static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm,            \
122     return addOperand(Inst, DAsm->DecoderName(Imm));                           \
129       MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,                           \
131     assert(Imm < (1 << 8) && "8-bit encoding");                                \
134         Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm));      \
139   static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,      \
141     assert(Imm < (1 << EncSize) && #EncSize "-bit encoding");                  \
151   DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0)
159                Imm | AMDGPU::EncValues::IS_VGPR, false, 0)
163   DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm, false, 0)
169   DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm | 512, false, 0)
174   DECODE_SrcOp(decodeOperand_##RegClass, 10, OpWidth, Imm, false, 0)
182   DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, Imm,      \
186   DECODE_SrcOp(decodeOperand_##Name, 9, OpWidth, Imm, false, ImmWidth)
192                Imm | 512, false, ImmWidth)
196                OpWidth, Imm, true, ImmWidth)
286 static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm,  in DECODE_OPERAND_REG_8()
289   assert(isUInt<10>(Imm) && "10-bit encoding expected");  in DECODE_OPERAND_REG_8()
290   assert((Imm & (1 << 8)) == 0 && "Imm{8} should not be used");  in DECODE_OPERAND_REG_8()
292   bool IsHi = Imm & (1 << 9);  in DECODE_OPERAND_REG_8()
293   unsigned RegIdx = Imm & 0xff;  in DECODE_OPERAND_REG_8()
299 DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,  in DecodeVGPR_16_Lo128RegisterClass()  argument
301   assert(isUInt<8>(Imm) && "8-bit encoding expected");  in DecodeVGPR_16_Lo128RegisterClass()
303   bool IsHi = Imm & (1 << 7);  in DecodeVGPR_16_Lo128RegisterClass()
304   unsigned RegIdx = Imm & 0x7f;  in DecodeVGPR_16_Lo128RegisterClass()
309 static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm,  in decodeOperand_VSrcT16_Lo128()  argument
312   assert(isUInt<9>(Imm) && "9-bit encoding expected");  in decodeOperand_VSrcT16_Lo128()
315   bool IsVGPR = Imm & (1 << 8);  in decodeOperand_VSrcT16_Lo128()
317     bool IsHi = Imm & (1 << 7);  in decodeOperand_VSrcT16_Lo128()
318     unsigned RegIdx = Imm & 0x7f;  in decodeOperand_VSrcT16_Lo128()
322                                                    Imm & 0xFF, false, 16));  in decodeOperand_VSrcT16_Lo128()
325 static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm,  in decodeOperand_VSrcT16()  argument
328   assert(isUInt<10>(Imm) && "10-bit encoding expected");  in decodeOperand_VSrcT16()
331   bool IsVGPR = Imm & (1 << 8);  in decodeOperand_VSrcT16()
333     bool IsHi = Imm & (1 << 9);  in decodeOperand_VSrcT16()
334     unsigned RegIdx = Imm & 0xff;  in decodeOperand_VSrcT16()
338                                                    Imm & 0xFF, false, 16));  in decodeOperand_VSrcT16()
341 static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm,  in decodeOperand_KImmFP()  argument
345   return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm));  in decodeOperand_KImmFP()
368 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm,  in decodeOperand_AVLdSt_Any()  argument
373     Imm &= 511;  in decodeOperand_AVLdSt_Any()
389         Imm |= 512;  in decodeOperand_AVLdSt_Any()
396         Imm |= 512;  in decodeOperand_AVLdSt_Any()
399   return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256));  in decodeOperand_AVLdSt_Any()
402 static DecodeStatus decodeOperand_VSrc_f64(MCInst &Inst, unsigned Imm,  in decodeOperand_VSrc_f64()  argument
405   assert(Imm < (1 << 9) && "9-bit encoding");  in decodeOperand_VSrc_f64()
408       Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm, false, 64, true));  in decodeOperand_VSrc_f64()
412 DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr,  in DecodeAVLdSt_32RegisterClass()  argument
414   return decodeOperand_AVLdSt_Any(Inst, Imm,  in DecodeAVLdSt_32RegisterClass()
419 DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr,  in DecodeAVLdSt_64RegisterClass()  argument
421   return decodeOperand_AVLdSt_Any(Inst, Imm,  in DecodeAVLdSt_64RegisterClass()
426 DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr,  in DecodeAVLdSt_96RegisterClass()  argument
428   return decodeOperand_AVLdSt_Any(Inst, Imm,  in DecodeAVLdSt_96RegisterClass()
433 DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr,  in DecodeAVLdSt_128RegisterClass()  argument
435   return decodeOperand_AVLdSt_Any(Inst, Imm,  in DecodeAVLdSt_128RegisterClass()
440 DecodeAVLdSt_160RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr,  in DecodeAVLdSt_160RegisterClass()  argument
442   return decodeOperand_AVLdSt_Any(Inst, Imm, AMDGPUDisassembler::OPW160,  in DecodeAVLdSt_160RegisterClass()
1367 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {  in decodeIntImmed()  argument
1370   assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);  in decodeIntImmed()
1371   return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ?  in decodeIntImmed()
1372     (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :  in decodeIntImmed()
1373     (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));  in decodeIntImmed()
1377 static int64_t getInlineImmVal32(unsigned Imm) {  in getInlineImmVal32()  argument
1378   switch (Imm) {  in getInlineImmVal32()
1402 static int64_t getInlineImmVal64(unsigned Imm) {  in getInlineImmVal64()  argument
1403   switch (Imm) {  in getInlineImmVal64()
1427 static int64_t getInlineImmVal16(unsigned Imm) {  in getInlineImmVal16()  argument
1428   switch (Imm) {  in getInlineImmVal16()
1452 MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm) {  in decodeFPImmed()  argument
1453   assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN  in decodeFPImmed()
1454       && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX);  in decodeFPImmed()
1463     return MCOperand::createImm(getInlineImmVal32(Imm));  in decodeFPImmed()
1465     return MCOperand::createImm(getInlineImmVal64(Imm));  in decodeFPImmed()
1467     return MCOperand::createImm(getInlineImmVal16(Imm));  in decodeFPImmed()