47 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI,  in AMDGPUDisassembler()  function in AMDGPUDisassembler
78   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);  in decodeSOPPBrTarget()
92   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);  in decodeSMEMOffset()
106   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);  in decodeBoolReg()
113   auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);  in decodeSplitBarrier()
121     auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);              \
132     auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);              \
142     auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);              \
144                       DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm,   \
294   auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);  in DECODE_OPERAND_REG_8()
305   auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);  in DecodeVGPR_16_Lo128RegisterClass()
314   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);  in decodeOperand_VSrcT16_Lo128()
321   return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16,  in decodeOperand_VSrcT16_Lo128()
330   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);  in decodeOperand_VSrcT16()
337   return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16,  in decodeOperand_VSrcT16()
344   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);  in decodeOperand_KImmFP()
350   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);  in decodeOperandVOPDDstY()
369                                              AMDGPUDisassembler::OpWidthTy Opw,  in decodeOperand_AVLdSt_Any()
371   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);  in decodeOperand_AVLdSt_Any()
406   auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);  in decodeOperand_VSrc_f64()
408       Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm, false, 64, true));  in decodeOperand_VSrc_f64()
415                                   AMDGPUDisassembler::OPW32, Decoder);  in DecodeAVLdSt_32RegisterClass()
422                                   AMDGPUDisassembler::OPW64, Decoder);  in DecodeAVLdSt_64RegisterClass()
429                                   AMDGPUDisassembler::OPW96, Decoder);  in DecodeAVLdSt_96RegisterClass()
436                                   AMDGPUDisassembler::OPW128, Decoder);  in DecodeAVLdSt_128RegisterClass()
442   return decodeOperand_AVLdSt_Any(Inst, Imm, AMDGPUDisassembler::OPW160,  in DecodeAVLdSt_160RegisterClass()
491 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,  in getInstruction()
844 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const {  in convertEXPInst()
854 DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const {  in convertVINTERPInst()
870 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const {  in convertSDWAInst()
929 bool AMDGPUDisassembler::isMacDPP(MCInst &MI) const {  in isMacDPP()
949 void AMDGPUDisassembler::convertMacDPPInst(MCInst &MI) const {  in convertMacDPPInst()
958 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const {  in convertDPP8Inst()
1001 DecodeStatus AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const {  in convertVOP3DPPInst()
1028 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {  in convertMIMGInst()
1179 DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const {  in convertVOP3PDPPInst()
1209 DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const {  in convertVOPCDPPInst()
1229 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI,  in convertFMAanyK()
1249 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {  in getRegClassName()
1255 MCOperand AMDGPUDisassembler::errOperand(unsigned V,  in errOperand()
1265 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {  in createRegOperand()
1270 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,  in createRegOperand()
1280 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID,  in createSRegOperand()
1329 MCOperand AMDGPUDisassembler::createVGPR16Operand(unsigned RegIdx,  in createVGPR16Operand()
1337 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const {  in decodeMandatoryLiteralConstant()
1350 MCOperand AMDGPUDisassembler::decodeLiteralConstant(bool ExtendFP64) const {  in decodeLiteralConstant()
1367 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {  in decodeIntImmed()
1452 MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm) {  in decodeFPImmed()
1473 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const {  in getVgprClassId()
1498 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const {  in getAgprClassId()
1524 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const {  in getSgprClassId()
1548 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {  in getTtmpClassId()
1570 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {  in getTTmpIdx()
1579 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val,  in decodeSrcOp()
1597 MCOperand AMDGPUDisassembler::decodeNonVGPRSrcOp(const OpWidthTy Width,  in decodeNonVGPRSrcOp()
1647 MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst,  in decodeVOPDDstYOp()
1655   auto Width = llvm::AMDGPUDisassembler::OPW32;  in decodeVOPDDstYOp()
1659 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {  in decodeSpecialReg32()
1695 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {  in decodeSpecialReg64()
1726 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width,  in decodeSDWASrc()
1768 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const {  in decodeSDWASrc16()
1772 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const {  in decodeSDWASrc32()
1776 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {  in decodeSDWAVopcDst()
1803 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const {  in decodeBoolReg()
1809 MCOperand AMDGPUDisassembler::decodeSplitBarrier(unsigned Val) const {  in decodeSplitBarrier()
1813 bool AMDGPUDisassembler::isVI() const {  in isVI()
1817 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); }  in isGFX9()
1819 bool AMDGPUDisassembler::isGFX90A() const {  in isGFX90A()
1823 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); }  in isGFX9Plus()
1825 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); }  in isGFX10()
1827 bool AMDGPUDisassembler::isGFX10Plus() const {  in isGFX10Plus()
1831 bool AMDGPUDisassembler::isGFX11() const {  in isGFX11()
1835 bool AMDGPUDisassembler::isGFX11Plus() const {  in isGFX11Plus()
1839 bool AMDGPUDisassembler::isGFX12Plus() const {  in isGFX12Plus()
1843 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const {  in hasArchitectedFlatScratch()
1847 bool AMDGPUDisassembler::hasKernargPreload() const {  in hasKernargPreload()
1866 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1(  in decodeCOMPUTE_PGM_RSRC1()
1978 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2(  in decodeCOMPUTE_PGM_RSRC2()
2032 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3(  in decodeCOMPUTE_PGM_RSRC3()
2112 AMDGPUDisassembler::decodeKernelDescriptorDirective(  in decodeKernelDescriptorDirective()
2261 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor(  in decodeKernelDescriptor()
2301 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size,  in onSymbolStart()
2380   return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo());  in createAMDGPUDisassembler()