5173     return TokError("directive only supported for amdgcn architecture");  in ParseDirectiveAMDGCNTarget()
5237     return TokError("directive only supported for amdgcn architecture");  in ParseDirectiveAMDHSAKernel()
5240     return TokError("directive only supported for amdhsa OS");  in ParseDirectiveAMDHSAKernel()
5283       return TokError(".amdhsa_ directives cannot be repeated");  in ParseDirectiveAMDHSAKernel()
5567     return TokError(".amdhsa_next_free_vgpr directive is required");  in ParseDirectiveAMDHSAKernel()
5570     return TokError(".amdhsa_next_free_sgpr directive is required");  in ParseDirectiveAMDHSAKernel()
5595     return TokError("amdgpu_user_sgpr_count smaller than than implied by "  in ParseDirectiveAMDHSAKernel()
5602     return TokError("too many user SGPRs enabled");  in ParseDirectiveAMDHSAKernel()
5608     return TokError("Kernarg preload length + offset is larger than the "  in ParseDirectiveAMDHSAKernel()
5613       return TokError(".amdhsa_accum_offset directive is required");  in ParseDirectiveAMDHSAKernel()
5615       return TokError("accum_offset should be in range [4..256] in "  in ParseDirectiveAMDHSAKernel()
5618       return TokError("accum_offset exceeds total VGPR allocation");  in ParseDirectiveAMDHSAKernel()
5626       return TokError("shared_vgpr_count directive not valid on "  in ParseDirectiveAMDHSAKernel()
5630       return TokError("shared_vgpr_count*2 + "  in ParseDirectiveAMDHSAKernel()
5663     return TokError(Err.str());  in ParseAMDKernelCodeTValue()
5670       return TokError("enable_dx10_clamp=1 is not allowed on GFX12+");  in ParseAMDKernelCodeTValue()
5676       return TokError("enable_ieee_mode=1 is not allowed on GFX12+");  in ParseAMDKernelCodeTValue()
5682         return TokError("enable_wavefront_size32=1 is only allowed on GFX10+");  in ParseAMDKernelCodeTValue()
5684         return TokError("enable_wavefront_size32=1 requires +WavefrontSize32");  in ParseAMDKernelCodeTValue()
5687         return TokError("enable_wavefront_size32=0 requires +WavefrontSize64");  in ParseAMDKernelCodeTValue()
5694         return TokError("wavefront_size=5 is only allowed on GFX10+");  in ParseAMDKernelCodeTValue()
5696         return TokError("wavefront_size=5 requires +WavefrontSize32");  in ParseAMDKernelCodeTValue()
5699         return TokError("wavefront_size=6 requires +WavefrontSize64");  in ParseAMDKernelCodeTValue()
5706       return TokError("enable_wgp_mode=1 is only allowed on GFX10+");  in ParseAMDKernelCodeTValue()
5712       return TokError("enable_mem_ordered=1 is only allowed on GFX10+");  in ParseAMDKernelCodeTValue()
5718       return TokError("enable_fwd_progress=1 is only allowed on GFX10+");  in ParseAMDKernelCodeTValue()
5823     return TokError(Twine("expected directive ") +  in ParseToEndDirective()
5857       return TokError(Twine("invalid value in ") +  in ParseDirectivePALMetadata()
5861       return TokError(Twine("expected an even number of values in ") +  in ParseDirectivePALMetadata()
5865       return TokError(Twine("invalid value in ") +  in ParseDirectivePALMetadata()
5884     return TokError("expected identifier in directive");  in ParseDirectiveAMDGPULDS()