Lines Matching refs:Operands
1374 void cvtMubufImpl(MCInst &Inst, const OperandVector &Operands,
1576 OperandVector &Operands, MCStreamer &Out,
1580 ParseStatus parseOperand(OperandVector &Operands, StringRef Mnemonic,
1584 SMLoc NameLoc, OperandVector &Operands) override;
1587 ParseStatus parseTokenOp(StringRef Name, OperandVector &Operands);
1592 parseIntWithPrefix(const char *Prefix, OperandVector &Operands,
1597 const char *Prefix, OperandVector &Operands,
1602 parseNamedBit(StringRef Name, OperandVector &Operands,
1605 ParseStatus parseCPol(OperandVector &Operands);
1606 ParseStatus parseScope(OperandVector &Operands, int64_t &Scope);
1607 ParseStatus parseTH(OperandVector &Operands, int64_t &TH);
1617 ParseStatus parseImm(OperandVector &Operands, bool HasSP3AbsModifier = false,
1619 ParseStatus parseReg(OperandVector &Operands);
1620 ParseStatus parseRegOrImm(OperandVector &Operands, bool HasSP3AbsMod = false,
1622 ParseStatus parseRegOrImmWithFPInputMods(OperandVector &Operands,
1624 ParseStatus parseRegOrImmWithIntInputMods(OperandVector &Operands,
1626 ParseStatus parseRegWithFPInputMods(OperandVector &Operands);
1627 ParseStatus parseRegWithIntInputMods(OperandVector &Operands);
1628 ParseStatus parseVReg32OrOff(OperandVector &Operands);
1629 ParseStatus tryParseIndexKey(OperandVector &Operands,
1631 ParseStatus parseIndexKey8bit(OperandVector &Operands);
1632 ParseStatus parseIndexKey16bit(OperandVector &Operands);
1640 ParseStatus parseFORMAT(OperandVector &Operands);
1643 ParseStatus parseFlatOffset(OperandVector &Operands);
1644 ParseStatus parseR128A16(OperandVector &Operands);
1645 ParseStatus parseBLGP(OperandVector &Operands);
1649 void cvtExp(MCInst &Inst, const OperandVector &Operands);
1652 ParseStatus parseSWaitCnt(OperandVector &Operands);
1656 ParseStatus parseDepCtr(OperandVector &Operands);
1659 ParseStatus parseSDelayALU(OperandVector &Operands);
1661 ParseStatus parseHwreg(OperandVector &Operands);
1685 SMLoc getFlatOffsetLoc(const OperandVector &Operands) const;
1686 SMLoc getSMEMOffsetLoc(const OperandVector &Operands) const;
1687 SMLoc getBLGPLoc(const OperandVector &Operands) const;
1690 const OperandVector &Operands) const;
1691 SMLoc getImmLoc(AMDGPUOperand::ImmTy Type, const OperandVector &Operands) const;
1692 SMLoc getRegLoc(unsigned Reg, const OperandVector &Operands) const;
1693 SMLoc getLitLoc(const OperandVector &Operands,
1695 SMLoc getMandatoryLitLoc(const OperandVector &Operands) const;
1696 SMLoc getConstLoc(const OperandVector &Operands) const;
1697 SMLoc getInstLoc(const OperandVector &Operands) const;
1699 bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands);
1700 bool validateOffset(const MCInst &Inst, const OperandVector &Operands);
1701 bool validateFlatOffset(const MCInst &Inst, const OperandVector &Operands);
1702 bool validateSMEMOffset(const MCInst &Inst, const OperandVector &Operands);
1704 bool validateConstantBusLimitations(const MCInst &Inst, const OperandVector &Operands);
1706 const OperandVector &Operands);
1710 bool validateMovrels(const MCInst &Inst, const OperandVector &Operands);
1717 bool validateDPP(const MCInst &Inst, const OperandVector &Operands);
1719 bool validateVOPLiteral(const MCInst &Inst, const OperandVector &Operands);
1720 bool validateMAIAccWrite(const MCInst &Inst, const OperandVector &Operands);
1721 bool validateMAISrc2(const MCInst &Inst, const OperandVector &Operands);
1722 bool validateMFMA(const MCInst &Inst, const OperandVector &Operands);
1725 bool validateBLGP(const MCInst &Inst, const OperandVector &Operands);
1726 bool validateDS(const MCInst &Inst, const OperandVector &Operands);
1727 bool validateGWS(const MCInst &Inst, const OperandVector &Operands);
1729 bool validateWaitCnt(const MCInst &Inst, const OperandVector &Operands);
1730 bool validateCoherencyBits(const MCInst &Inst, const OperandVector &Operands,
1732 bool validateTHAndScopeBits(const MCInst &Inst, const OperandVector &Operands,
1734 bool validateExeczVcczOperands(const OperandVector &Operands);
1735 bool validateTFE(const MCInst &Inst, const OperandVector &Operands);
1764 bool parseExpr(OperandVector &Operands);
1774 ParseStatus parseCustomOperand(OperandVector &Operands, unsigned MCK);
1776 ParseStatus parseExpTgt(OperandVector &Operands);
1777 ParseStatus parseSendMsg(OperandVector &Operands);
1778 ParseStatus parseInterpSlot(OperandVector &Operands);
1779 ParseStatus parseInterpAttr(OperandVector &Operands);
1780 ParseStatus parseSOPPBrTarget(OperandVector &Operands);
1781 ParseStatus parseBoolReg(OperandVector &Operands);
1792 ParseStatus parseSwizzle(OperandVector &Operands);
1801 ParseStatus parseGPRIdxMode(OperandVector &Operands);
1804 …void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false); } in cvtMubuf() argument
1805 …void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, tr… in cvtMubufAtomic() argument
1807 ParseStatus parseOModSI(OperandVector &Operands);
1809 void cvtVOP3(MCInst &Inst, const OperandVector &Operands,
1811 void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands);
1812 void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
1813 void cvtVOP3P(MCInst &Inst, const OperandVector &Operands);
1814 void cvtSWMMAC(MCInst &Inst, const OperandVector &Operands);
1816 void cvtVOPD(MCInst &Inst, const OperandVector &Operands);
1817 void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands,
1819 void cvtVOP3P(MCInst &Inst, const OperandVector &Operands,
1822 void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands);
1823 void cvtVINTERP(MCInst &Inst, const OperandVector &Operands);
1826 ParseStatus parseDim(OperandVector &Operands);
1828 ParseStatus parseDPP8(OperandVector &Operands);
1829 ParseStatus parseDPPCtrl(OperandVector &Operands);
1830 bool isSupportedDPPCtrl(StringRef Ctrl, const OperandVector &Operands);
1833 void cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8 = false);
1834 void cvtDPP8(MCInst &Inst, const OperandVector &Operands) { in cvtDPP8() argument
1835 cvtDPP(Inst, Operands, true); in cvtDPP8()
1837 void cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,
1839 void cvtVOP3DPP8(MCInst &Inst, const OperandVector &Operands) { in cvtVOP3DPP8() argument
1840 cvtVOP3DPP(Inst, Operands, true); in cvtVOP3DPP8()
1843 ParseStatus parseSDWASel(OperandVector &Operands, StringRef Prefix,
1845 ParseStatus parseSDWADstUnused(OperandVector &Operands);
1846 void cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands);
1847 void cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands);
1848 void cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands);
1849 void cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands);
1850 void cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands);
1851 void cvtSDWA(MCInst &Inst, const OperandVector &Operands,
1856 ParseStatus parseEndpgm(OperandVector &Operands);
1858 ParseStatus parseVOPD(OperandVector &Operands);
2983 ParseStatus AMDGPUAsmParser::parseImm(OperandVector &Operands, in parseImm() argument
2996 ParseStatus S = parseImm(Operands, HasSP3AbsModifier, HasLit); in parseImm()
3034 Operands.push_back( in parseImm()
3037 AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back()); in parseImm()
3064 Operands.push_back(AMDGPUOperand::CreateImm(this, IntVal, S)); in parseImm()
3065 AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back()); in parseImm()
3070 Operands.push_back(AMDGPUOperand::CreateExpr(this, Expr, S)); in parseImm()
3079 ParseStatus AMDGPUAsmParser::parseReg(OperandVector &Operands) { in parseReg() argument
3085 Operands.push_back(std::move(R)); in parseReg()
3091 ParseStatus AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands, in parseRegOrImm() argument
3093 ParseStatus Res = parseReg(Operands); in parseRegOrImm()
3098 return parseImm(Operands, HasSP3AbsMod, HasLit); in parseRegOrImm()
3190 AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands, in parseRegOrImmWithFPInputMods() argument
3225 Res = parseRegOrImm(Operands, SP3Abs, Lit); in parseRegOrImmWithFPInputMods()
3227 Res = parseReg(Operands); in parseRegOrImmWithFPInputMods()
3232 if (Lit && !Operands.back()->isImm()) in parseRegOrImmWithFPInputMods()
3250 AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back()); in parseRegOrImmWithFPInputMods()
3259 AMDGPUAsmParser::parseRegOrImmWithIntInputMods(OperandVector &Operands, in parseRegOrImmWithIntInputMods() argument
3267 Res = parseRegOrImm(Operands); in parseRegOrImmWithIntInputMods()
3269 Res = parseReg(Operands); in parseRegOrImmWithIntInputMods()
3281 AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back()); in parseRegOrImmWithIntInputMods()
3290 ParseStatus AMDGPUAsmParser::parseRegWithFPInputMods(OperandVector &Operands) { in parseRegWithFPInputMods() argument
3291 return parseRegOrImmWithFPInputMods(Operands, false); in parseRegWithFPInputMods()
3294 ParseStatus AMDGPUAsmParser::parseRegWithIntInputMods(OperandVector &Operands) { in parseRegWithIntInputMods() argument
3295 return parseRegOrImmWithIntInputMods(Operands, false); in parseRegWithIntInputMods()
3298 ParseStatus AMDGPUAsmParser::parseVReg32OrOff(OperandVector &Operands) { in parseVReg32OrOff() argument
3301 Operands.push_back(AMDGPUOperand::CreateImm(this, 0, Loc, in parseVReg32OrOff()
3311 Operands.push_back(std::move(Reg)); in parseVReg32OrOff()
3544 const MCInst &Inst, const OperandVector &Operands) { in validateConstantBusLimitations() argument
3622 SMLoc LitLoc = getLitLoc(Operands); in validateConstantBusLimitations()
3623 SMLoc RegLoc = getRegLoc(LastSGPR, Operands); in validateConstantBusLimitations()
3630 const MCInst &Inst, const OperandVector &Operands) { in validateVOPDRegBankConstraints() argument
3658 assert(ParsedIdx > 0 && ParsedIdx < Operands.size()); in validateVOPDRegBankConstraints()
3660 auto Loc = ((AMDGPUOperand &)*Operands[ParsedIdx]).getStartLoc(); in validateVOPDRegBankConstraints()
3883 const OperandVector &Operands) { in validateMovrels() argument
3901 ErrLoc = getRegLoc(Reg, Operands); in validateMovrels()
3903 ErrLoc = getConstLoc(Operands); in validateMovrels()
3911 const OperandVector &Operands) { in validateMAIAccWrite() argument
3928 Error(getRegLoc(Reg, Operands), in validateMAIAccWrite()
3937 const OperandVector &Operands) { in validateMAISrc2() argument
3950 Error(getConstLoc(Operands), in validateMAISrc2()
3959 const OperandVector &Operands) { in validateMFMA() argument
3984 Error(getRegLoc(mc2PseudoReg(Src2Reg), Operands), in validateMFMA()
4200 SMLoc AMDGPUAsmParser::getFlatOffsetLoc(const OperandVector &Operands) const { in getFlatOffsetLoc()
4201 for (unsigned i = 1, e = Operands.size(); i != e; ++i) { in getFlatOffsetLoc()
4202 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); in getFlatOffsetLoc()
4210 const OperandVector &Operands) { in validateOffset() argument
4218 return validateFlatOffset(Inst, Operands); in validateOffset()
4221 return validateSMEMOffset(Inst, Operands); in validateOffset()
4228 Error(getFlatOffsetLoc(Operands), in validateOffset()
4235 Error(getFlatOffsetLoc(Operands), in validateOffset()
4244 const OperandVector &Operands) { in validateFlatOffset() argument
4255 Error(getFlatOffsetLoc(Operands), in validateFlatOffset()
4267 Error(getFlatOffsetLoc(Operands), in validateFlatOffset()
4277 SMLoc AMDGPUAsmParser::getSMEMOffsetLoc(const OperandVector &Operands) const { in getSMEMOffsetLoc()
4279 for (unsigned i = 2, e = Operands.size(); i != e; ++i) { in getSMEMOffsetLoc()
4280 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); in getSMEMOffsetLoc()
4288 const OperandVector &Operands) { in validateSMEMOffset() argument
4311 Error(getSMEMOffsetLoc(Operands), in validateSMEMOffset()
4432 const OperandVector &Operands) { in validateDPP() argument
4441 SMLoc S = getImmLoc(AMDGPUOperand::ImmTyDppCtrl, Operands); in validateDPP()
4457 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[Src1Idx]); in validateDPP()
4476 const OperandVector &Operands) { in validateVOPLiteral() argument
4507 Error(getLitLoc(Operands), "invalid operand for instruction"); in validateVOPLiteral()
4528 Error(getLitLoc(Operands), "literal operands are not supported"); in validateVOPLiteral()
4533 Error(getLitLoc(Operands, true), "only one unique literal operand is allowed"); in validateVOPLiteral()
4613 SMLoc AMDGPUAsmParser::getBLGPLoc(const OperandVector &Operands) const { in getBLGPLoc()
4614 for (unsigned i = 1, e = Operands.size(); i != e; ++i) { in getBLGPLoc()
4615 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); in getBLGPLoc()
4623 const OperandVector &Operands) { in validateBLGP() argument
4628 SMLoc BLGPLoc = getBLGPLoc(Operands); in validateBLGP()
4655 const OperandVector &Operands) { in validateWaitCnt() argument
4672 SMLoc RegLoc = getRegLoc(Reg, Operands); in validateWaitCnt()
4678 const OperandVector &Operands) { in validateDS() argument
4683 return validateGWS(Inst, Operands); in validateDS()
4693 SMLoc S = getImmLoc(AMDGPUOperand::ImmTyGDS, Operands); in validateDS()
4703 const OperandVector &Operands) { in validateGWS() argument
4720 SMLoc RegLoc = getRegLoc(Reg, Operands); in validateGWS()
4729 const OperandVector &Operands, in validateCoherencyBits() argument
4739 return validateTHAndScopeBits(Inst, Operands, CPol); in validateCoherencyBits()
4744 SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands); in validateCoherencyBits()
4759 SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands); in validateCoherencyBits()
4779 SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands); in validateCoherencyBits()
4793 const OperandVector &Operands, in validateTHAndScopeBits() argument
4802 SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands); in validateTHAndScopeBits()
4846 bool AMDGPUAsmParser::validateExeczVcczOperands(const OperandVector &Operands) { in validateExeczVcczOperands() argument
4849 for (auto &Operand : Operands) { in validateExeczVcczOperands()
4854 Error(getRegLoc(Reg, Operands), in validateExeczVcczOperands()
4863 const OperandVector &Operands) { in validateTFE() argument
4867 SMLoc Loc = getImmLoc(AMDGPUOperand::ImmTyTFE, Operands); in validateTFE()
4868 if (Loc != getInstLoc(Operands)) { in validateTFE()
4879 const OperandVector &Operands) { in validateInstruction() argument
4881 Error(getRegLoc(LDS_DIRECT, Operands), *ErrMsg); in validateInstruction()
4885 Error(getLitLoc(Operands), in validateInstruction()
4889 if (!validateVOPLiteral(Inst, Operands)) { in validateInstruction()
4892 if (!validateConstantBusLimitations(Inst, Operands)) { in validateInstruction()
4895 if (!validateVOPDRegBankConstraints(Inst, Operands)) { in validateInstruction()
4899 Error(getImmLoc(AMDGPUOperand::ImmTyClampSI, Operands), in validateInstruction()
4904 Error(getImmLoc(AMDGPUOperand::ImmTyOpSel, Operands), in validateInstruction()
4909 Error(getImmLoc(AMDGPUOperand::ImmTyNegLo, Operands), in validateInstruction()
4914 Error(getImmLoc(AMDGPUOperand::ImmTyNegHi, Operands), in validateInstruction()
4918 if (!validateDPP(Inst, Operands)) { in validateInstruction()
4923 Error(getImmLoc(AMDGPUOperand::ImmTyD16, Operands), in validateInstruction()
4928 Error(getImmLoc(AMDGPUOperand::ImmTyDim, Operands), in validateInstruction()
4938 Error(getImmLoc(AMDGPUOperand::ImmTyDMask, Operands), in validateInstruction()
4943 Error(getImmLoc(AMDGPUOperand::ImmTyDMask, Operands), in validateInstruction()
4947 if (!validateMovrels(Inst, Operands)) { in validateInstruction()
4950 if (!validateOffset(Inst, Operands)) { in validateInstruction()
4953 if (!validateMAIAccWrite(Inst, Operands)) { in validateInstruction()
4956 if (!validateMAISrc2(Inst, Operands)) { in validateInstruction()
4959 if (!validateMFMA(Inst, Operands)) { in validateInstruction()
4962 if (!validateCoherencyBits(Inst, Operands, IDLoc)) { in validateInstruction()
4978 if (!validateDS(Inst, Operands)) { in validateInstruction()
4982 if (!validateBLGP(Inst, Operands)) { in validateInstruction()
4990 if (!validateWaitCnt(Inst, Operands)) { in validateInstruction()
4993 if (!validateExeczVcczOperands(Operands)) { in validateInstruction()
4996 if (!validateTFE(Inst, Operands)) { in validateInstruction()
5072 static bool isInvalidVOPDY(const OperandVector &Operands, in isInvalidVOPDY() argument
5074 assert(InvalidOprIdx < Operands.size()); in isInvalidVOPDY()
5075 const auto &Op = ((AMDGPUOperand &)*Operands[InvalidOprIdx]); in isInvalidVOPDY()
5077 const auto &PrevOp = ((AMDGPUOperand &)*Operands[InvalidOprIdx - 1]); in isInvalidVOPDY()
5084 OperandVector &Operands, in MatchAndEmitInstruction() argument
5092 auto R = MatchInstructionImpl(Operands, Inst, EI, MatchingInlineAsm, in MatchAndEmitInstruction()
5113 if (!validateInstruction(Inst, IDLoc, Operands)) { in MatchAndEmitInstruction()
5121 StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken(); in MatchAndEmitInstruction()
5137 if (ErrorInfo >= Operands.size()) { in MatchAndEmitInstruction()
5140 ErrorLoc = ((AMDGPUOperand &)*Operands[ErrorInfo]).getStartLoc(); in MatchAndEmitInstruction()
5144 if (isInvalidVOPDY(Operands, ErrorInfo)) in MatchAndEmitInstruction()
6037 ParseStatus AMDGPUAsmParser::parseOperand(OperandVector &Operands, in parseOperand() argument
6040 ParseStatus Res = parseVOPD(Operands); in parseOperand()
6045 Res = MatchOperandParserImpl(Operands, Mnemonic); in parseOperand()
6059 unsigned Prefix = Operands.size(); in parseOperand()
6063 Res = parseReg(Operands); in parseOperand()
6078 if (Operands.size() - Prefix > 1) { in parseOperand()
6079 Operands.insert(Operands.begin() + Prefix, in parseOperand()
6081 Operands.push_back(AMDGPUOperand::CreateToken(this, "]", RBraceLoc)); in parseOperand()
6087 return parseRegOrImm(Operands); in parseOperand()
6122 SMLoc NameLoc, OperandVector &Operands) { in ParseInstruction() argument
6130 Operands.push_back(AMDGPUOperand::CreateToken(this, Name, NameLoc)); in ParseInstruction()
6136 if (IsMIMG && isGFX10Plus() && Operands.size() == 2) in ParseInstruction()
6138 ParseStatus Res = parseOperand(Operands, Name, Mode); in ParseInstruction()
6166 OperandVector &Operands) { in parseTokenOp() argument
6171 Operands.push_back(AMDGPUOperand::CreateToken(this, Name, S)); in parseTokenOp()
6185 const char *Prefix, OperandVector &Operands, AMDGPUOperand::ImmTy ImmTy, in parseIntWithPrefix() argument
6198 Operands.push_back(AMDGPUOperand::CreateImm(this, Value, S, ImmTy)); in parseIntWithPrefix()
6203 const char *Prefix, OperandVector &Operands, AMDGPUOperand::ImmTy ImmTy, in parseOperandArrayWithPrefix() argument
6238 Operands.push_back(AMDGPUOperand::CreateImm(this, Val, S, ImmTy)); in parseOperandArrayWithPrefix()
6243 OperandVector &Operands, in parseNamedBit() argument
6264 Operands.push_back(AMDGPUOperand::CreateImm(this, Bit, S, ImmTy)); in parseNamedBit()
6288 ParseStatus AMDGPUAsmParser::parseCPol(OperandVector &Operands) { in parseCPol() argument
6299 ResTH = parseTH(Operands, TH); in parseCPol()
6310 ResScope = parseScope(Operands, Scope); in parseCPol()
6325 Operands.push_back(AMDGPUOperand::CreateImm(this, CPolVal, StringLoc, in parseCPol()
6330 StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken(); in parseCPol()
6360 Operands.push_back( in parseCPol()
6365 ParseStatus AMDGPUAsmParser::parseScope(OperandVector &Operands, in parseScope() argument
6390 ParseStatus AMDGPUAsmParser::parseTH(OperandVector &Operands, int64_t &TH) { in parseTH() argument
6455 MCInst& Inst, const OperandVector& Operands, in addOptionalImmOperand() argument
6462 ((AMDGPUOperand &)*Operands[Idx]).addImmOperands(Inst, 1); in addOptionalImmOperand()
6504 ParseStatus AMDGPUAsmParser::tryParseIndexKey(OperandVector &Operands, in tryParseIndexKey() argument
6519 Operands.push_back(AMDGPUOperand::CreateImm(this, ImmVal, Loc, ImmTy)); in tryParseIndexKey()
6523 ParseStatus AMDGPUAsmParser::parseIndexKey8bit(OperandVector &Operands) { in parseIndexKey8bit() argument
6524 return tryParseIndexKey(Operands, AMDGPUOperand::ImmTyIndexKey8bit); in parseIndexKey8bit()
6527 ParseStatus AMDGPUAsmParser::parseIndexKey16bit(OperandVector &Operands) { in parseIndexKey16bit() argument
6528 return tryParseIndexKey(Operands, AMDGPUOperand::ImmTyIndexKey16bit); in parseIndexKey16bit()
6695 ParseStatus AMDGPUAsmParser::parseFORMAT(OperandVector &Operands) { in parseFORMAT() argument
6709 Operands.push_back( in parseFORMAT()
6722 Res = parseRegOrImm(Operands); in parseFORMAT()
6733 auto Size = Operands.size(); in parseFORMAT()
6734 AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands[Size - 2]); in parseFORMAT()
6746 ParseStatus AMDGPUAsmParser::parseFlatOffset(OperandVector &Operands) { in parseFlatOffset() argument
6748 parseIntWithPrefix("offset", Operands, AMDGPUOperand::ImmTyOffset); in parseFlatOffset()
6750 Res = parseIntWithPrefix("inst_offset", Operands, in parseFlatOffset()
6756 ParseStatus AMDGPUAsmParser::parseR128A16(OperandVector &Operands) { in parseR128A16() argument
6758 parseNamedBit("r128", Operands, AMDGPUOperand::ImmTyR128A16); in parseR128A16()
6760 Res = parseNamedBit("a16", Operands, AMDGPUOperand::ImmTyA16); in parseR128A16()
6764 ParseStatus AMDGPUAsmParser::parseBLGP(OperandVector &Operands) { in parseBLGP() argument
6766 parseIntWithPrefix("blgp", Operands, AMDGPUOperand::ImmTyBLGP); in parseBLGP()
6769 parseOperandArrayWithPrefix("neg", Operands, AMDGPUOperand::ImmTyBLGP); in parseBLGP()
6778 void AMDGPUAsmParser::cvtExp(MCInst &Inst, const OperandVector &Operands) { in cvtExp() argument
6785 for (unsigned i = 1, e = Operands.size(); i != e; ++i) { in cvtExp()
6786 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); in cvtExp()
6833 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpVM); in cvtExp()
6834 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpCompr); in cvtExp()
6913 ParseStatus AMDGPUAsmParser::parseSWaitCnt(OperandVector &Operands) { in parseSWaitCnt() argument
6928 Operands.push_back(AMDGPUOperand::CreateImm(this, Waitcnt, S)); in parseSWaitCnt()
6994 ParseStatus AMDGPUAsmParser::parseSDelayALU(OperandVector &Operands) { in parseSDelayALU() argument
7008 Operands.push_back(AMDGPUOperand::CreateImm(this, Delay, S)); in parseSDelayALU()
7081 ParseStatus AMDGPUAsmParser::parseDepCtr(OperandVector &Operands) { in parseDepCtr() argument
7098 Operands.push_back(AMDGPUOperand::CreateImm(this, DepCtr, Loc)); in parseDepCtr()
7175 ParseStatus AMDGPUAsmParser::parseHwreg(OperandVector &Operands) { in parseHwreg() argument
7198 Operands.push_back(AMDGPUOperand::CreateImm(this, ImmVal, Loc, AMDGPUOperand::ImmTyHwreg)); in parseHwreg()
7292 ParseStatus AMDGPUAsmParser::parseSendMsg(OperandVector &Operands) { in parseSendMsg() argument
7315 Operands.push_back(AMDGPUOperand::CreateImm(this, ImmVal, Loc, AMDGPUOperand::ImmTySendMsg)); in parseSendMsg()
7327 ParseStatus AMDGPUAsmParser::parseInterpSlot(OperandVector &Operands) { in parseInterpSlot() argument
7343 Operands.push_back(AMDGPUOperand::CreateImm(this, Slot, S, in parseInterpSlot()
7348 ParseStatus AMDGPUAsmParser::parseInterpAttr(OperandVector &Operands) { in parseInterpAttr() argument
7379 Operands.push_back(AMDGPUOperand::CreateImm(this, Attr, S, in parseInterpAttr()
7381 Operands.push_back(AMDGPUOperand::CreateImm( in parseInterpAttr()
7390 ParseStatus AMDGPUAsmParser::parseExpTgt(OperandVector &Operands) { in parseExpTgt() argument
7405 Operands.push_back(AMDGPUOperand::CreateImm(this, Id, S, in parseExpTgt()
7504 AMDGPUAsmParser::parseExpr(OperandVector &Operands) { in parseExpr() argument
7513 Operands.push_back(AMDGPUOperand::CreateImm(this, IntVal, S)); in parseExpr()
7515 Operands.push_back(AMDGPUOperand::CreateExpr(this, Expr, S)); in parseExpr()
7584 SMLoc AMDGPUAsmParser::getInstLoc(const OperandVector &Operands) const { in getInstLoc()
7585 return ((AMDGPUOperand &)*Operands[0]).getStartLoc(); in getInstLoc()
7590 const OperandVector &Operands) const { in getOperandLoc()
7591 for (unsigned i = Operands.size() - 1; i > 0; --i) { in getOperandLoc()
7592 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); in getOperandLoc()
7596 return getInstLoc(Operands); in getOperandLoc()
7601 const OperandVector &Operands) const { in getImmLoc()
7603 return getOperandLoc(Test, Operands); in getImmLoc()
7608 const OperandVector &Operands) const { in getRegLoc()
7612 return getOperandLoc(Test, Operands); in getRegLoc()
7615 SMLoc AMDGPUAsmParser::getLitLoc(const OperandVector &Operands, in getLitLoc() argument
7620 SMLoc Loc = getOperandLoc(Test, Operands); in getLitLoc()
7621 if (SearchMandatoryLiterals && Loc == getInstLoc(Operands)) in getLitLoc()
7622 Loc = getMandatoryLitLoc(Operands); in getLitLoc()
7626 SMLoc AMDGPUAsmParser::getMandatoryLitLoc(const OperandVector &Operands) const { in getMandatoryLitLoc()
7630 return getOperandLoc(Test, Operands); in getMandatoryLitLoc()
7634 AMDGPUAsmParser::getConstLoc(const OperandVector &Operands) const { in getConstLoc()
7638 return getOperandLoc(Test, Operands); in getConstLoc()
7872 ParseStatus AMDGPUAsmParser::parseSwizzle(OperandVector &Operands) { in parseSwizzle() argument
7887 Operands.push_back(AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTySwizzle)); in parseSwizzle()
7947 ParseStatus AMDGPUAsmParser::parseGPRIdxMode(OperandVector &Operands) { in parseGPRIdxMode() argument
7965 Operands.push_back( in parseGPRIdxMode()
7978 ParseStatus AMDGPUAsmParser::parseSOPPBrTarget(OperandVector &Operands) { in parseSOPPBrTarget() argument
7986 if (!parseExpr(Operands)) in parseSOPPBrTarget()
7989 AMDGPUOperand &Opr = ((AMDGPUOperand &)*Operands[Operands.size() - 1]); in parseSOPPBrTarget()
8008 ParseStatus AMDGPUAsmParser::parseBoolReg(OperandVector &Operands) { in parseBoolReg() argument
8009 return parseReg(Operands); in parseBoolReg()
8017 const OperandVector &Operands, in cvtMubufImpl() argument
8024 for (unsigned i = FirstOperandIdx, e = Operands.size(); i != e; ++i) { in cvtMubufImpl()
8025 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); in cvtMubufImpl()
8042 for (unsigned i = FirstOperandIdx, e = Operands.size(); i != e; ++i) { in cvtMubufImpl()
8043 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); in cvtMubufImpl()
8073 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset); in cvtMubufImpl()
8074 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCPol, 0); in cvtMubufImpl()
8147 ParseStatus AMDGPUAsmParser::parseOModSI(OperandVector &Operands) { in parseOModSI() argument
8150 return parseIntWithPrefix("mul", Operands, in parseOModSI()
8155 return parseIntWithPrefix("div", Operands, in parseOModSI()
8189 const OperandVector &Operands) { in cvtVOP3OpSel() argument
8190 cvtVOP3P(Inst, Operands); in cvtVOP3OpSel()
8194 void AMDGPUAsmParser::cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands, in cvtVOP3OpSel() argument
8196 cvtVOP3P(Inst, Operands, OptionalIdx); in cvtVOP3OpSel()
8213 void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands) in cvtVOP3Interp() argument
8221 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1); in cvtVOP3Interp()
8224 for (unsigned E = Operands.size(); I != E; ++I) { in cvtVOP3Interp()
8225 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]); in cvtVOP3Interp()
8239 addOptionalImmOperand(Inst, Operands, OptionalIdx, in cvtVOP3Interp()
8243 addOptionalImmOperand(Inst, Operands, OptionalIdx, in cvtVOP3Interp()
8247 addOptionalImmOperand(Inst, Operands, OptionalIdx, in cvtVOP3Interp()
8251 void AMDGPUAsmParser::cvtVINTERP(MCInst &Inst, const OperandVector &Operands) in cvtVINTERP() argument
8259 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1); in cvtVINTERP()
8262 for (unsigned E = Operands.size(); I != E; ++I) { in cvtVINTERP()
8263 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]); in cvtVINTERP()
8273 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI); in cvtVINTERP()
8277 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOpSel); in cvtVINTERP()
8279 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyWaitEXP); in cvtVINTERP()
8311 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands, in cvtVOP3() argument
8318 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1); in cvtVOP3()
8321 for (unsigned E = Operands.size(); I != E; ++I) { in cvtVOP3()
8322 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]); in cvtVOP3()
8335 addOptionalImmOperand(Inst, Operands, OptionalIdx, in cvtVOP3()
8339 addOptionalImmOperand(Inst, Operands, OptionalIdx, in cvtVOP3()
8356 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) { in cvtVOP3() argument
8358 cvtVOP3(Inst, Operands, OptionalIdx); in cvtVOP3()
8361 void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands, in cvtVOP3P() argument
8392 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSel); in cvtVOP3P()
8398 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSelHi, in cvtVOP3P()
8404 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegLo); in cvtVOP3P()
8408 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegHi); in cvtVOP3P()
8462 void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) { in cvtVOP3P() argument
8464 cvtVOP3(Inst, Operands, OptIdx); in cvtVOP3P()
8465 cvtVOP3P(Inst, Operands, OptIdx); in cvtVOP3P()
8468 static void addSrcModifiersAndSrc(MCInst &Inst, const OperandVector &Operands, in addSrcModifiersAndSrc() argument
8471 ((AMDGPUOperand &)*Operands[i]).addRegOrImmWithFPInputModsOperands(Inst, 2); in addSrcModifiersAndSrc()
8473 ((AMDGPUOperand &)*Operands[i]).addRegOperands(Inst, 1); in addSrcModifiersAndSrc()
8476 void AMDGPUAsmParser::cvtSWMMAC(MCInst &Inst, const OperandVector &Operands) { in cvtSWMMAC() argument
8479 ((AMDGPUOperand &)*Operands[1]).addRegOperands(Inst, 1); in cvtSWMMAC()
8480 addSrcModifiersAndSrc(Inst, Operands, 2, Opc, AMDGPU::OpName::src0_modifiers); in cvtSWMMAC()
8481 addSrcModifiersAndSrc(Inst, Operands, 3, Opc, AMDGPU::OpName::src1_modifiers); in cvtSWMMAC()
8482 ((AMDGPUOperand &)*Operands[1]).addRegOperands(Inst, 1); // srcTiedDef in cvtSWMMAC()
8483 ((AMDGPUOperand &)*Operands[4]).addRegOperands(Inst, 1); // src2 in cvtSWMMAC()
8486 for (unsigned i = 5; i < Operands.size(); ++i) { in cvtSWMMAC()
8487 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); in cvtSWMMAC()
8492 addOptionalImmOperand(Inst, Operands, OptIdx, in cvtSWMMAC()
8496 addOptionalImmOperand(Inst, Operands, OptIdx, in cvtSWMMAC()
8500 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyClampSI); in cvtSWMMAC()
8502 cvtVOP3P(Inst, Operands, OptIdx); in cvtSWMMAC()
8509 ParseStatus AMDGPUAsmParser::parseVOPD(OperandVector &Operands) { in parseVOPD() argument
8517 Operands.push_back(AMDGPUOperand::CreateToken(this, "::", S)); in parseVOPD()
8521 Operands.push_back(AMDGPUOperand::CreateToken(this, OpYName, OpYLoc)); in parseVOPD()
8530 void AMDGPUAsmParser::cvtVOPD(MCInst &Inst, const OperandVector &Operands) { in cvtVOPD() argument
8532 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[ParsedOprIdx]); in cvtVOPD()
8652 ParseStatus AMDGPUAsmParser::parseDim(OperandVector &Operands) { in parseDim() argument
8666 Operands.push_back(AMDGPUOperand::CreateImm(this, Encoding, S, in parseDim()
8675 ParseStatus AMDGPUAsmParser::parseDPP8(OperandVector &Operands) { in parseDPP8() argument
8706 Operands.push_back(AMDGPUOperand::CreateImm(this, DPP8, S, AMDGPUOperand::ImmTyDPP8)); in parseDPP8()
8712 const OperandVector &Operands) { in isSupportedDPPCtrl() argument
8813 ParseStatus AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) { in parseDPPCtrl() argument
8817 !isSupportedDPPCtrl(getTokenStr(), Operands)) in parseDPPCtrl()
8843 Operands.push_back( in parseDPPCtrl()
8848 void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands, in cvtVOP3DPP() argument
8865 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1); in cvtVOP3DPP()
8869 for (unsigned E = Operands.size(); I != E; ++I) { in cvtVOP3DPP()
8906 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]); in cvtVOP3DPP()
8925 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI); in cvtVOP3DPP()
8928 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI); in cvtVOP3DPP()
8931 cvtVOP3P(Inst, Operands, OptionalIdx); in cvtVOP3DPP()
8933 cvtVOP3OpSel(Inst, Operands, OptionalIdx); in cvtVOP3DPP()
8935 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOpSel); in cvtVOP3DPP()
8939 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDPP8); in cvtVOP3DPP()
8943 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppCtrl, 0xe4); in cvtVOP3DPP()
8944 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf); in cvtVOP3DPP()
8945 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf); in cvtVOP3DPP()
8946 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl); in cvtVOP3DPP()
8949 addOptionalImmOperand(Inst, Operands, OptionalIdx, in cvtVOP3DPP()
8954 void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8) { in cvtDPP() argument
8960 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1); in cvtDPP()
8964 for (unsigned E = Operands.size(); I != E; ++I) { in cvtDPP()
8972 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]); in cvtDPP()
9012 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf); in cvtDPP()
9013 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf); in cvtDPP()
9014 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl); in cvtDPP()
9016 addOptionalImmOperand(Inst, Operands, OptionalIdx, in cvtDPP()
9026 ParseStatus AMDGPUAsmParser::parseSDWASel(OperandVector &Operands, in parseSDWASel() argument
9053 Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, Type)); in parseSDWASel()
9057 ParseStatus AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) { in parseSDWADstUnused() argument
9078 Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, AMDGPUOperand::ImmTySDWADstUnused)); in parseSDWADstUnused()
9082 void AMDGPUAsmParser::cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands) { in cvtSdwaVOP1() argument
9083 cvtSDWA(Inst, Operands, SIInstrFlags::VOP1); in cvtSdwaVOP1()
9086 void AMDGPUAsmParser::cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands) { in cvtSdwaVOP2() argument
9087 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2); in cvtSdwaVOP2()
9090 void AMDGPUAsmParser::cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands) { in cvtSdwaVOP2b() argument
9091 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, true, true); in cvtSdwaVOP2b()
9094 void AMDGPUAsmParser::cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands) { in cvtSdwaVOP2e() argument
9095 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, false, true); in cvtSdwaVOP2e()
9098 void AMDGPUAsmParser::cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands) { in cvtSdwaVOPC() argument
9099 cvtSDWA(Inst, Operands, SIInstrFlags::VOPC, isVI()); in cvtSdwaVOPC()
9102 void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands, in cvtSDWA() argument
9115 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1); in cvtSDWA()
9118 for (unsigned E = Operands.size(); I != E; ++I) { in cvtSDWA()
9119 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]); in cvtSDWA()
9156 addOptionalImmOperand(Inst, Operands, OptionalIdx, in cvtSDWA()
9160 addOptionalImmOperand(Inst, Operands, OptionalIdx, in cvtSDWA()
9164 addOptionalImmOperand(Inst, Operands, OptionalIdx, in cvtSDWA()
9168 addOptionalImmOperand(Inst, Operands, OptionalIdx, in cvtSDWA()
9172 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD… in cvtSDWA()
9176 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0); in cvtSDWA()
9179 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI, 0); in cvtSDWA()
9181 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWADstSel, SdwaSel::DWORD); in cvtSDWA()
9182 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWADstUnused, DstUnused::U… in cvtSDWA()
9183 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD… in cvtSDWA()
9184 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc1Sel, SdwaSel::DWORD… in cvtSDWA()
9189 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0); in cvtSDWA()
9190 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD… in cvtSDWA()
9191 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc1Sel, SdwaSel::DWORD… in cvtSDWA()
9222 ParseStatus AMDGPUAsmParser::parseCustomOperand(OperandVector &Operands, in parseCustomOperand() argument
9226 return parseTokenOp("addr64", Operands); in parseCustomOperand()
9228 return parseTokenOp("done", Operands); in parseCustomOperand()
9230 return parseTokenOp("idxen", Operands); in parseCustomOperand()
9232 return parseTokenOp("lds", Operands); in parseCustomOperand()
9234 return parseTokenOp("offen", Operands); in parseCustomOperand()
9236 return parseTokenOp("off", Operands); in parseCustomOperand()
9238 return parseTokenOp("row_en", Operands); in parseCustomOperand()
9240 return parseNamedBit("gds", Operands, AMDGPUOperand::ImmTyGDS); in parseCustomOperand()
9242 return parseNamedBit("tfe", Operands, AMDGPUOperand::ImmTyTFE); in parseCustomOperand()
9244 return tryCustomParseOperand(Operands, MCK); in parseCustomOperand()
9306 ParseStatus AMDGPUAsmParser::parseEndpgm(OperandVector &Operands) { in parseEndpgm() argument
9318 Operands.push_back( in parseEndpgm()