1575   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1699   bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands);
1711   bool validateMIMGDataSize(const MCInst &Inst, const SMLoc &IDLoc);
1712   bool validateMIMGAddrSize(const MCInst &Inst, const SMLoc &IDLoc);
1731                              const SMLoc &IDLoc);
1747   bool checkUnsupportedInstruction(StringRef Name, const SMLoc &IDLoc);
3690                                            const SMLoc &IDLoc) {  in validateMIMGDataSize()  argument
3732   Error(IDLoc, Twine("image data size does not match ") + Modifiers);  in validateMIMGDataSize()
3737                                            const SMLoc &IDLoc) {  in validateMIMGAddrSize()  argument
3763     Error(IDLoc, "image address size does not match a16");  in validateMIMGAddrSize()
3801   Error(IDLoc, "image address size does not match dim and a16");  in validateMIMGAddrSize()
4730                                             const SMLoc &IDLoc) {  in validateCoherencyBits()  argument
4749       Error(IDLoc, "invalid cache policy for SMEM instruction");  in validateCoherencyBits()
4773       Error(IDLoc, isGFX940() ? "instruction must use sc0"  in validateCoherencyBits()
4878                                           const SMLoc &IDLoc,  in validateInstruction()  argument
4932   if (!validateMIMGDataSize(Inst, IDLoc)) {  in validateInstruction()
4935   if (!validateMIMGAddrSize(Inst, IDLoc))  in validateInstruction()
4962   if (!validateCoherencyBits(Inst, Operands, IDLoc)) {  in validateInstruction()
4967     Error(IDLoc, getFeatureBits()[AMDGPU::FeatureGFX90AInsts]  in validateInstruction()
4974     Error(IDLoc,  in validateInstruction()
4987     Error(IDLoc, "ABS not allowed in VOP3B instructions");  in validateInstruction()
5028                                                   const SMLoc &IDLoc) {  in checkUnsupportedInstruction()  argument
5043     return Error(IDLoc,  in checkUnsupportedInstruction()
5059       return Error(IDLoc, "instruction requires wavesize=32");  in checkUnsupportedInstruction()
5064     return Error(IDLoc, "instruction not supported on this GPU");  in checkUnsupportedInstruction()
5069   return Error(IDLoc, "invalid instruction" + Suggestion);  in checkUnsupportedInstruction()
5083 bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,  in MatchAndEmitInstruction()  argument
5113     if (!validateInstruction(Inst, IDLoc, Operands)) {  in MatchAndEmitInstruction()
5116     Inst.setLoc(IDLoc);  in MatchAndEmitInstruction()
5122   if (checkUnsupportedInstruction(Mnemo, IDLoc)) {  in MatchAndEmitInstruction()
5132     return Error(IDLoc, "operands are not valid for this GPU or mode");  in MatchAndEmitInstruction()
5135     SMLoc ErrorLoc = IDLoc;  in MatchAndEmitInstruction()
5138         return Error(IDLoc, "too few operands for instruction");  in MatchAndEmitInstruction()
5142         ErrorLoc = IDLoc;  in MatchAndEmitInstruction()
5151     return Error(IDLoc, "internal error: instruction without _e64 suffix "  in MatchAndEmitInstruction()