904   return getStandardCSEConfigForOpt(TM->getOptLevel());  in getCSEConfig()
985   if (getOptLevel() == CodeGenOptLevel::Aggressive)  in addEarlyCSEOrGVNPass()
1045   if (TM.getOptLevel() > CodeGenOptLevel::None)  in addIRPasses()
1048   if (TM.getOptLevel() > CodeGenOptLevel::None)  in addIRPasses()
1053       (TM.getOptLevel() >= CodeGenOptLevel::Less) &&  in addIRPasses()
1060   if (TM.getOptLevel() > CodeGenOptLevel::None) {  in addIRPasses()
1082     if (TM.getOptLevel() > CodeGenOptLevel::Less)  in addIRPasses()
1128   if (TM->getOptLevel() > CodeGenOptLevel::None)  in addPreISel()
1134   addPass(createAMDGPUISelDag(getAMDGPUTargetMachine(), getOptLevel()));  in addInstSelector()
1179   if (TM->getOptLevel() > CodeGenOptLevel::None)  in addPreISel()
1182   if (TM->getOptLevel() > CodeGenOptLevel::None)  in addPreISel()
1205   if (TM->getOptLevel() > CodeGenOptLevel::Less)  in addPreISel()
1251   addPass(new IRTranslator(getOptLevel()));  in addIRTranslator()
1256   bool IsOptNone = getOptLevel() == CodeGenOptLevel::None;  in addPreLegalizeMachineIR()
1267   bool IsOptNone = getOptLevel() == CodeGenOptLevel::None;  in addPreRegBankSelect()
1278   bool IsOptNone = getOptLevel() == CodeGenOptLevel::None;  in addPreGlobalInstructionSelect()
1283   addPass(new InstructionSelect(getOptLevel()));  in addGlobalInstructionSelect()
1323   if (TM->getOptLevel() > CodeGenOptLevel::Less)  in addOptimizedRegAlloc()
1435   if (getOptLevel() > CodeGenOptLevel::None)  in addPostRegAlloc()
1441   if (TM->getOptLevel() > CodeGenOptLevel::None)  in addPreSched2()
1454   if (getOptLevel() > CodeGenOptLevel::None)  in addPreEmitPass()
1460   if (getOptLevel() > CodeGenOptLevel::None)  in addPreEmitPass()