158       const RegisterBank *DstBank = RBI.getRegBank(DstReg, MRI, *RBI.TRI);  in applyBank()  local
159       assert(DstBank != &AMDGPU::VCCRegBank);  in applyBank()
1064   const RegisterBank *DstBank =  in applyMappingLoad()  local
1066   if (DstBank == &AMDGPU::SGPRRegBank) {  in applyMappingLoad()
1091     ApplyRegBankMapping ApplyBank(B, *this, MRI, DstBank);  in applyMappingLoad()
1467   const RegisterBank *DstBank =  in applyMappingBFE()  local
1469   if (DstBank == &AMDGPU::VGPRRegBank) {  in applyMappingBFE()
1622   const RegisterBank &DstBank =  in applyMappingMAD_64_32()  local
1654     MRI.setRegBank(Src2Lo, DstBank);  in applyMappingMAD_64_32()
1655     MRI.setRegBank(Src2Hi, DstBank);  in applyMappingMAD_64_32()
1668     MRI.setRegBank(DstLo, DstBank);  in applyMappingMAD_64_32()
1673     MRI.setRegBank(DstHi, DstBank);  in applyMappingMAD_64_32()
1945   const RegisterBank &DstBank =  in foldExtractEltToCmpSelect()  local
1951     (DstBank == AMDGPU::SGPRRegBank &&  in foldExtractEltToCmpSelect()
1986         MRI.setRegBank(S->getOperand(N).getReg(), DstBank);  in foldExtractEltToCmpSelect()
1995     MRI.setRegBank(DstReg, DstBank);  in foldExtractEltToCmpSelect()
1998   MRI.setRegBank(MI.getOperand(0).getReg(), DstBank);  in foldExtractEltToCmpSelect()
2043   const RegisterBank &DstBank =  in foldInsertEltToCmpSelect()  local
2051     (DstBank == AMDGPU::SGPRRegBank &&  in foldInsertEltToCmpSelect()
2083       Register Op0 = constrainRegToBank(MRI, B, InsRegs[L], DstBank);  in foldInsertEltToCmpSelect()
2085       Op1 = constrainRegToBank(MRI, B, Op1, DstBank);  in foldInsertEltToCmpSelect()
2088       MRI.setRegBank(Select, DstBank);  in foldInsertEltToCmpSelect()
2099     MRI.setRegBank(Vec->getOperand(0).getReg(), DstBank);  in foldInsertEltToCmpSelect()
2103   MRI.setRegBank(MI.getOperand(0).getReg(), DstBank);  in foldInsertEltToCmpSelect()
2191     const RegisterBank *DstBank =  in applyMappingImpl()  local
2193     if (DstBank == &AMDGPU::VCCRegBank)  in applyMappingImpl()
2211     MRI.setRegBank(NewDstReg, *DstBank);  in applyMappingImpl()
2222     const RegisterBank *DstBank =  in applyMappingImpl()  local
2224     if (DstBank == &AMDGPU::VCCRegBank) {  in applyMappingImpl()
2252     ApplyRegBankMapping ApplyBank(B, *this, MRI, DstBank);  in applyMappingImpl()
2276     const RegisterBank *DstBank =  in applyMappingImpl()  local
2278     if (DstBank != &AMDGPU::SGPRRegBank)  in applyMappingImpl()
2391       const RegisterBank *DstBank =  in applyMappingImpl()  local
2393       if (DstBank == &AMDGPU::VCCRegBank)  in applyMappingImpl()
2397       ApplyRegBankMapping ApplyBank(B, *this, MRI, DstBank);  in applyMappingImpl()
2490     const RegisterBank *DstBank =  in applyMappingImpl()  local
2492     if (DstBank == &AMDGPU::VGPRRegBank)  in applyMappingImpl()
2563     const RegisterBank *DstBank =  in applyMappingImpl()  local
2568     if (DstBank == &AMDGPU::SGPRRegBank) {  in applyMappingImpl()
2649     const RegisterBank *DstBank =  in applyMappingImpl()  local
2651     if (DstBank == &AMDGPU::SGPRRegBank)  in applyMappingImpl()
2673     const RegisterBank *DstBank =  in applyMappingImpl()  local
2675     if (DstBank == &AMDGPU::SGPRRegBank)  in applyMappingImpl()
2758       const RegisterBank *DstBank = &AMDGPU::VGPRRegBank;  in applyMappingImpl()  local
2770       MRI.setRegBank(True.getReg(0), *DstBank);  in applyMappingImpl()
2771       MRI.setRegBank(False.getReg(0), *DstBank);  in applyMappingImpl()
2772       MRI.setRegBank(DstReg, *DstBank);  in applyMappingImpl()
2779         MRI.setRegBank(Sel.getReg(0), *DstBank);  in applyMappingImpl()
2808     const RegisterBank *DstBank = DstMapping.BreakDown[0].RegBank;  in applyMappingImpl()  local
2835     const bool NeedCopyToVGPR = DstBank == &AMDGPU::VGPRRegBank &&  in applyMappingImpl()
2882     MRI.setRegBank(DstReg, *DstBank);  in applyMappingImpl()
2995     const RegisterBank *DstBank =  in applyMappingImpl()  local
3004     MRI.setRegBank(InsLo.getReg(0), *DstBank);  in applyMappingImpl()
3005     MRI.setRegBank(InsHi.getReg(0), *DstBank);  in applyMappingImpl()
3734     const RegisterBank *DstBank = getRegBank(MI.getOperand(0).getReg(), MRI,  in getInstrMapping()  local
3739     if (!DstBank)  in getInstrMapping()
3740       DstBank = SrcBank;  in getInstrMapping()
3744         cannotCopy(*DstBank, *SrcBank, TypeSize::getFixed(Size)))  in getInstrMapping()
3747     const ValueMapping &ValMap = getValueMapping(0, Size, *DstBank);  in getInstrMapping()
3790     if (const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI))  in getInstrMapping()  local
3791       ResultBank = DstBank->getID();  in getInstrMapping()
3835       const RegisterBank *DstBank  in getInstrMapping()  local
3841       if (DstBank) {  in getInstrMapping()
3842         TargetBankID = DstBank->getID();  in getInstrMapping()
3843         if (DstBank == &AMDGPU::VCCRegBank) {  in getInstrMapping()
4183     unsigned DstBank;  in getInstrMapping()  local
4188       DstBank = AMDGPU::SGPRRegBankID;  in getInstrMapping()
4191       DstBank = AMDGPU::VGPRRegBankID;  in getInstrMapping()
4197     OpdsMapping[0] = AMDGPU::getValueMappingSGPR64Only(DstBank, DstSize);  in getInstrMapping()
4228     unsigned DstBank = getRegBankID(MI.getOperand(0).getReg(), MRI,  in getInstrMapping()  local
4246     bool CanUseSCC = DstBank == AMDGPU::SGPRRegBankID &&  in getInstrMapping()
4251     DstBank = CanUseSCC ? AMDGPU::SGPRRegBankID : AMDGPU::VCCRegBankID;  in getInstrMapping()
4258     OpdsMapping[0] = AMDGPU::getValueMapping(DstBank, ResultSize);  in getInstrMapping()