163         Register MaskedReg = MRI->createVirtualRegister(SrcRC);  in selectCOPY()
255   Register DstReg = MRI->createVirtualRegister(&SubRC);  in getSubOperand64()
353     Register UnusedCarry = MRI->createVirtualRegister(TRI.getWaveMaskRegClass());  in selectG_ADD_SUB()
376   Register DstLo = MRI->createVirtualRegister(&HalfRC);  in selectG_ADD_SUB()
377   Register DstHi = MRI->createVirtualRegister(&HalfRC);  in selectG_ADD_SUB()
389     Register CarryReg = MRI->createVirtualRegister(CarryRC);  in selectG_ADD_SUB()
396       .addDef(MRI->createVirtualRegister(CarryRC), RegState::Dead)  in selectG_ADD_SUB()
707     Register TmpReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectG_BUILD_VECTOR()
898   Register InterpMov = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectInterpP1F16()
1437     Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectBallot()
1719     Register M0Base = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectDSGWSIntrinsic()
1998       Register TmpReg = MRI->createVirtualRegister(  in selectImageIntrinsic()
2061     Register Zero = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectImageIntrinsic()
2075       Register Undef = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectImageIntrinsic()
2287     Register LoReg = MRI->createVirtualRegister(DstRC);  in selectG_TRUNC()
2288     Register HiReg = MRI->createVirtualRegister(DstRC);  in selectG_TRUNC()
2308       Register TmpReg0 = MRI->createVirtualRegister(DstRC);  in selectG_TRUNC()
2309       Register TmpReg1 = MRI->createVirtualRegister(DstRC);  in selectG_TRUNC()
2310       Register ImmReg = MRI->createVirtualRegister(DstRC);  in selectG_TRUNC()
2423     Register UndefReg = MRI->createVirtualRegister(SrcRC);  in selectG_SZA_EXT()
2478       Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_SZA_EXT()
2505       Register ExtReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass);  in selectG_SZA_EXT()
2506       Register UndefReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_SZA_EXT()
2636     Register LoReg = MRI->createVirtualRegister(RC);  in selectG_CONSTANT()
2637     Register HiReg = MRI->createVirtualRegister(RC);  in selectG_CONSTANT()
2691   Register LoReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FNEG()
2692   Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FNEG()
2693   Register ConstReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FNEG()
2694   Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FNEG()
2729   Register LoReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FABS()
2730   Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FABS()
2731   Register ConstReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FABS()
2732   Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_FABS()
2911       Register TmpReg = MRI->createVirtualRegister(TRI.getBoolRC());  in selectG_BRCOND()
3012   Register HiReg = MRI->createVirtualRegister(&RegRC);  in selectG_PTRMASK()
3013   Register LoReg = MRI->createVirtualRegister(&RegRC);  in selectG_PTRMASK()
3028     Register MaskLo = MRI->createVirtualRegister(&RegRC);  in selectG_PTRMASK()
3029     MaskedLo = MRI->createVirtualRegister(&RegRC);  in selectG_PTRMASK()
3042     Register MaskHi = MRI->createVirtualRegister(&RegRC);  in selectG_PTRMASK()
3043     MaskedHi = MRI->createVirtualRegister(&RegRC);  in selectG_PTRMASK()
3288     Register IdxReg = MRI->createVirtualRegister(TRI.getVGPR64Class());  in selectBufferLoadLds()
3398       VOffset = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectGlobalLoadLds()
3540     WaveAddr = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectStackRestore()
3979                  .addDef(MRI.createVirtualRegister(DstRegClass));  in buildRegSequence()
4271     *SOffset = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectSmrdOffset()
4432                 MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectGlobalSAddr()
4498   Register VOffset = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectGlobalSAddr()
4551       SAddr = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectScratchSAddr()
4656     Register HighBits = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectMUBUFScratchOffen()
5047   Register RSrc2 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);  in buildRSRC()
5048   Register RSrc3 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);  in buildRSRC()
5049   Register RSrcHi = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);  in buildRSRC()
5050   Register RSrc = MRI.createVirtualRegister(&AMDGPU::SGPR_128RegClass);  in buildRSRC()
5071     RSrcLo = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);  in buildRSRC()
5156   SOffset = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in splitIllegalMUBUFOffset()
5593     TmpReg0 = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectNamedBarrierInst()
5608       Register TmpReg1 = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectNamedBarrierInst()