124   return RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI) &&  in constrainCopyLikeIntrin()
125          RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI);  in constrainCopyLikeIntrin()
144       return RBI.constrainGenericRegister(DstReg, *RC, *MRI);  in selectCOPY()
149       if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI))  in selectCOPY()
191     if (RC && !RBI.constrainGenericRegister(DstReg, *RC, *MRI))  in selectCOPY()
205     RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI);  in selectCOPY()
245   return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI);  in selectPHI()
413   if (!RBI.constrainGenericRegister(DstReg, RC, *MRI))  in selectG_ADD_SUB()
466   if (!RBI.constrainGenericRegister(Dst0Reg, AMDGPU::SReg_32RegClass, *MRI) ||  in selectG_UADDO_USUBO_UADDE_USUBE()
467       !RBI.constrainGenericRegister(Src0Reg, AMDGPU::SReg_32RegClass, *MRI) ||  in selectG_UADDO_USUBO_UADDE_USUBE()
468       !RBI.constrainGenericRegister(Src1Reg, AMDGPU::SReg_32RegClass, *MRI))  in selectG_UADDO_USUBO_UADDE_USUBE()
472       !RBI.constrainGenericRegister(I.getOperand(4).getReg(),  in selectG_UADDO_USUBO_UADDE_USUBE()
520   if (!DstRC || !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI))  in selectG_EXTRACT()
572     if (SrcRC && !RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI))  in selectG_MERGE_VALUES()
576   if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI))  in selectG_MERGE_VALUES()
601   if (!SrcRC || !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))  in selectG_UNMERGE_VALUES()
615     if (!SrcRC || !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))  in selectG_UNMERGE_VALUES()
620     if (DstRC && !RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI))  in selectG_UNMERGE_VALUES()
679         return RBI.constrainGenericRegister(Dst, AMDGPU::VGPR_32RegClass, *MRI);  in selectG_BUILD_VECTOR()
685       return RBI.constrainGenericRegister(Dst, AMDGPU::SReg_32RegClass, *MRI);  in selectG_BUILD_VECTOR()
701     return RBI.constrainGenericRegister(Dst, RC, *MRI) &&  in selectG_BUILD_VECTOR()
702            RBI.constrainGenericRegister(Src0, RC, *MRI);  in selectG_BUILD_VECTOR()
788       (RC && RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI))) {  in selectG_IMPLICIT_DEF()
840   if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) ||  in selectG_INSERT()
841       !RBI.constrainGenericRegister(Src0Reg, *Src0RC, *MRI) ||  in selectG_INSERT()
842       !RBI.constrainGenericRegister(Src1Reg, *Src1RC, *MRI))  in selectG_INSERT()
886   if (!RBI.constrainGenericRegister(M0Val, AMDGPU::SReg_32RegClass, *MRI) ||  in selectInterpP1F16()
887       !RBI.constrainGenericRegister(Dst, AMDGPU::VGPR_32RegClass, *MRI) ||  in selectInterpP1F16()
888       !RBI.constrainGenericRegister(Src0, AMDGPU::VGPR_32RegClass, *MRI))  in selectInterpP1F16()
967       RBI.constrainGenericRegister(LaneSelect, AMDGPU::SReg_32_XM0RegClass, *MRI);  in selectWritelane()
1332         RBI.constrainGenericRegister(CCReg, AMDGPU::SReg_32RegClass, *MRI);  in selectG_ICMP_or_FCMP()
1348   RBI.constrainGenericRegister(ICmp->getOperand(0).getReg(),  in selectG_ICMP_or_FCMP()
1377     return RBI.constrainGenericRegister(Dst, *TRI.getBoolRC(), *MRI);  in selectIntrinsicCmp()
1405   RBI.constrainGenericRegister(Dst, *TRI.getBoolRC(), *MRI);  in selectIntrinsicCmp()
1477   if (!DstRC || !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI))  in selectRelocConstant()
1536       !RBI.constrainGenericRegister(DstReg, *RC, *MRI))  in selectReturnAddress()
1633   if (!RBI.constrainGenericRegister(M0Val, AMDGPU::SReg_32RegClass, *MRI))  in selectDSOrderedIntrinsic()
1708       if (!RBI.constrainGenericRegister(BaseOffset, AMDGPU::VGPR_32RegClass, *MRI))  in selectDSGWSIntrinsic()
1714       if (!RBI.constrainGenericRegister(BaseOffset,  in selectDSGWSIntrinsic()
1738     if (!RBI.constrainGenericRegister(VSrc, AMDGPU::VGPR_32RegClass, *MRI))  in selectDSGWSIntrinsic()
1772   if (!RBI.constrainGenericRegister(PtrBase, AMDGPU::SReg_32RegClass, *MRI))  in selectDSAppendConsume()
2277   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI) ||  in selectG_TRUNC()
2278       !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) {  in selectG_TRUNC()
2361       if (!RBI.constrainGenericRegister(SrcReg, *SrcWithSubRC, *MRI))  in selectG_TRUNC()
2432     return RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) &&  in selectG_SZA_EXT()
2433            RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI);  in selectG_SZA_EXT()
2463     if (!RBI.constrainGenericRegister(SrcReg, SrcRC, *MRI))  in selectG_SZA_EXT()
2472       return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, *MRI);  in selectG_SZA_EXT()
2495       return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_64RegClass,  in selectG_SZA_EXT()
2521       return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_64RegClass, *MRI);  in selectG_SZA_EXT()
2537     return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, *MRI);  in selectG_SZA_EXT()
2572       return RBI.constrainGenericRegister(Dst, AMDGPU::SReg_32RegClass, *MRI);  in selectG_FPEXT()
2659   return RBI.constrainGenericRegister(DstReg, *DstRC, *MRI);  in selectG_CONSTANT()
2685   if (!RBI.constrainGenericRegister(Src, AMDGPU::SReg_64RegClass, *MRI) ||  in selectG_FNEG()
2686       !RBI.constrainGenericRegister(Dst, AMDGPU::SReg_64RegClass, *MRI))  in selectG_FNEG()
2734   if (!RBI.constrainGenericRegister(Src, AMDGPU::SReg_64RegClass, *MRI) ||  in selectG_FABS()
2735       !RBI.constrainGenericRegister(Dst, AMDGPU::SReg_64RegClass, *MRI))  in selectG_FABS()
2945   return RBI.constrainGenericRegister(  in selectG_GLOBAL_VALUE()
2993   if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) ||  in selectG_PTRMASK()
2994       !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI) ||  in selectG_PTRMASK()
2995       !RBI.constrainGenericRegister(MaskReg, *MaskRC, *MRI))  in selectG_PTRMASK()
3112   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI) ||  in selectG_EXTRACT_VECTOR_ELT()
3113       !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) ||  in selectG_EXTRACT_VECTOR_ELT()
3114       !RBI.constrainGenericRegister(IdxReg, AMDGPU::SReg_32RegClass, *MRI))  in selectG_EXTRACT_VECTOR_ELT()
3193   if (!RBI.constrainGenericRegister(VecReg, *VecRC, *MRI) ||  in selectG_INSERT_VECTOR_ELT()
3194       !RBI.constrainGenericRegister(DstReg, *VecRC, *MRI) ||  in selectG_INSERT_VECTOR_ELT()
3195       !RBI.constrainGenericRegister(ValReg, *ValRC, *MRI) ||  in selectG_INSERT_VECTOR_ELT()
3196       !RBI.constrainGenericRegister(IdxReg, AMDGPU::SReg_32RegClass, *MRI))  in selectG_INSERT_VECTOR_ELT()
3520   if (!RBI.constrainGenericRegister(DstReg, RC, *MRI))  in selectWaveAddress()
3529   if (!RBI.constrainGenericRegister(SrcReg, AMDGPU::SReg_32RegClass, *MRI))  in selectStackRestore()
5544   return RBI.constrainGenericRegister(CCReg, AMDGPU::SReg_32_XM0_XEXECRegClass,  in selectSBarrierSignalIsfirst()
5648   return RBI.constrainGenericRegister(CCReg, AMDGPU::SReg_32_XM0_XEXECRegClass,  in selectSBarrierLeave()