885   Register M0Val = MI.getOperand(6).getReg();  in selectInterpP1F16()  local
886   if (!RBI.constrainGenericRegister(M0Val, AMDGPU::SReg_32RegClass, *MRI) ||  in selectInterpP1F16()
903     .addReg(M0Val);  in selectInterpP1F16()
1621   Register M0Val = MI.getOperand(2).getReg();  in selectDSOrderedIntrinsic()  local
1623     .addReg(M0Val);  in selectDSOrderedIntrinsic()
1633   if (!RBI.constrainGenericRegister(M0Val, AMDGPU::SReg_32RegClass, *MRI))  in selectDSOrderedIntrinsic()
5587   Register M0Val;  in selectNamedBarrierInst()  local
5599     M0Val = TmpReg0;  in selectNamedBarrierInst()
5612       M0Val = TmpReg1;  in selectNamedBarrierInst()
5614       M0Val = BarOp.getReg();  in selectNamedBarrierInst()
5619   if (M0Val) {  in selectNamedBarrierInst()
5621         BuildMI(*MBB, &I, DL, TII.get(AMDGPU::COPY), AMDGPU::M0).addReg(M0Val);  in selectNamedBarrierInst()