283 static unsigned getLogicalBitOpcode(unsigned Opc, bool Is64) {  in getLogicalBitOpcode()  argument
286     return Is64 ? AMDGPU::S_AND_B64 : AMDGPU::S_AND_B32;  in getLogicalBitOpcode()
288     return Is64 ? AMDGPU::S_OR_B64 : AMDGPU::S_OR_B32;  in getLogicalBitOpcode()
290     return Is64 ? AMDGPU::S_XOR_B64 : AMDGPU::S_XOR_B32;  in getLogicalBitOpcode()
305   bool Is64 = Size > 32 || (DstRB->getID() == AMDGPU::VCCRegBankID &&  in selectG_AND_OR_XOR()  local
307   I.setDesc(TII.get(getLogicalBitOpcode(I.getOpcode(), Is64)));  in selectG_AND_OR_XOR()
1418   const bool Is64 = Size == 64;  in selectBallot()  local
1423   if (Size != STI.getWavefrontSize() && (!Is64 || !IsWave32))  in selectBallot()
1449       unsigned Opcode = Is64 ? AMDGPU::S_MOV_B64 : AMDGPU::S_MOV_B32;  in selectBallot()
1996       const bool Is64 = MRI->getType(VDataOut).getSizeInBits() == 64;  in selectImageIntrinsic()  local
1999         Is64 ? &AMDGPU::VReg_128RegClass : &AMDGPU::VReg_64RegClass);  in selectImageIntrinsic()
2000       unsigned SubReg = Is64 ? AMDGPU::sub0_sub1 : AMDGPU::sub0;  in selectImageIntrinsic()
2907       const bool Is64 = STI.isWave64();  in selectG_BRCOND()  local
2908       const unsigned Opcode = Is64 ? AMDGPU::S_AND_B64 : AMDGPU::S_AND_B32;  in selectG_BRCOND()
2909       const Register Exec = Is64 ? AMDGPU::EXEC : AMDGPU::EXEC_LO;  in selectG_BRCOND()
3119   const bool Is64 = DstTy.getSizeInBits() == 64;  in selectG_EXTRACT_VECTOR_ELT()  local
3126     if (DstTy.getSizeInBits() != 32 && !Is64)  in selectG_EXTRACT_VECTOR_ELT()
3132     unsigned Opc = Is64 ? AMDGPU::S_MOVRELS_B64 : AMDGPU::S_MOVRELS_B32;  in selectG_EXTRACT_VECTOR_ELT()