Lines Matching refs:DstBank
555 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_MERGE_VALUES() local
558 TRI.getRegClassForSizeOnBank(DstSize, *DstBank); in selectG_MERGE_VALUES()
650 const RegisterBank *DstBank = RBI.getRegBank(Dst, *MRI, TRI); in selectG_BUILD_VECTOR() local
651 if (DstBank->getID() == AMDGPU::AGPRRegBankID) in selectG_BUILD_VECTOR()
654 assert(DstBank->getID() == AMDGPU::SGPRRegBankID || in selectG_BUILD_VECTOR()
655 DstBank->getID() == AMDGPU::VGPRRegBankID); in selectG_BUILD_VECTOR()
656 const bool IsVector = DstBank->getID() == AMDGPU::VGPRRegBankID; in selectG_BUILD_VECTOR()
821 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_INSERT() local
823 TRI.getRegClassForSizeOnBank(DstSize, *DstBank); in selectG_INSERT()
1475 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectRelocConstant() local
1476 const TargetRegisterClass *DstRC = TRI.getRegClassForSizeOnBank(32, *DstBank); in selectRelocConstant()
1480 const bool IsVALU = DstBank->getID() == AMDGPU::VGPRRegBankID; in selectRelocConstant()
2419 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_SZA_EXT() local
2421 TRI.getRegClassForSizeOnBank(DstSize, *DstBank); in selectG_SZA_EXT()