Lines Matching refs:CCReg
1320 Register CCReg = I.getOperand(0).getReg(); in selectG_ICMP_or_FCMP() local
1321 if (!isVCC(CCReg, *MRI)) { in selectG_ICMP_or_FCMP()
1328 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), CCReg) in selectG_ICMP_or_FCMP()
1332 RBI.constrainGenericRegister(CCReg, AMDGPU::SReg_32RegClass, *MRI); in selectG_ICMP_or_FCMP()
2185 Register CCReg = CCOp.getReg(); in selectG_SELECT() local
2186 if (!isVCC(CCReg, *MRI)) { in selectG_SELECT()
2190 .addReg(CCReg); in selectG_SELECT()
2195 if (!MRI->getRegClassOrNull(CCReg)) in selectG_SELECT()
2196 MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI)); in selectG_SELECT()
5526 Register CCReg = I.getOperand(0).getReg(); in selectSBarrierSignalIsfirst() local
5541 BuildMI(*MBB, &I, DL, TII.get(AMDGPU::COPY), CCReg).addReg(AMDGPU::SCC); in selectSBarrierSignalIsfirst()
5544 return RBI.constrainGenericRegister(CCReg, AMDGPU::SReg_32_XM0_XEXECRegClass, in selectSBarrierSignalIsfirst()
5642 Register CCReg = I.getOperand(0).getReg(); in selectSBarrierLeave() local
5645 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), CCReg).addReg(AMDGPU::SCC); in selectSBarrierLeave()
5648 return RBI.constrainGenericRegister(CCReg, AMDGPU::SReg_32_XM0_XEXECRegClass, in selectSBarrierLeave()