Lines Matching refs:node
9 // This file contains DAG node definitions for the AMDGPU target.
112 // This argument to this node is a dword address.
390 // Intrinsic/Custom node compatibility PatFrags
393 def AMDGPUrcp : PatFrags<(ops node:$src), [(int_amdgcn_rcp node:$src),
394 (AMDGPUrcp_impl node:$src)]>;
395 def AMDGPUrcp_legacy : PatFrags<(ops node:$src), [(int_amdgcn_rcp_legacy node:$src),
396 (AMDGPUrcp_legacy_impl node:$src)]>;
398 def AMDGPUrsq : PatFrags<(ops node:$src), [(int_amdgcn_rsq node:$src),
399 (AMDGPUrsq_impl node:$src)]>;
401 def AMDGPUrsq_clamp : PatFrags<(ops node:$src), [(int_amdgcn_rsq_clamp node:$src),
402 (AMDGPUrsq_clamp_impl node:$src)]>;
404 def AMDGPUsin : PatFrags<(ops node:$src), [(int_amdgcn_sin node:$src),
405 (AMDGPUsin_impl node:$src)]>;
406 def AMDGPUcos : PatFrags<(ops node:$src), [(int_amdgcn_cos node:$src),
407 (AMDGPUcos_impl node:$src)]>;
408 def AMDGPUfract : PatFrags<(ops node:$src), [(int_amdgcn_fract node:$src),
409 (AMDGPUfract_impl node:$src)]>;
410 def AMDGPUlog : PatFrags<(ops node:$src), [(int_amdgcn_log node:$src),
411 (AMDGPUlog_impl node:$src)]>;
412 def AMDGPUlogf16 : PatFrags<(ops node:$src), [(int_amdgcn_log node:$src),
413 (flog2 node:$src)]>;
415 def AMDGPUexp : PatFrags<(ops node:$src), [(int_amdgcn_exp2 node:$src),
416 (AMDGPUexp_impl node:$src)]>;
417 def AMDGPUexpf16 : PatFrags<(ops node:$src), [(int_amdgcn_exp2 node:$src),
418 (fexp2 node:$src)]>;
420 def AMDGPUfp_class : PatFrags<(ops node:$src0, node:$src1),
421 [(int_amdgcn_class node:$src0, node:$src1),
422 (AMDGPUfp_class_impl node:$src0, node:$src1)]>;
424 def AMDGPUfmed3 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
425 [(int_amdgcn_fmed3 node:$src0, node:$src1, node:$src2),
426 (AMDGPUfmed3_impl node:$src0, node:$src1, node:$src2)]>;
428 def AMDGPUdiv_fixup : PatFrags<(ops node:$src0, node:$src1, node:$src2),
429 [(int_amdgcn_div_fixup node:$src0, node:$src1, node:$src2),
430 (AMDGPUdiv_fixup_impl node:$src0, node:$src1, node:$src2)]>;
432 def AMDGPUffbh_i32 : PatFrags<(ops node:$src),
433 [(int_amdgcn_sffbh node:$src),
434 (AMDGPUffbh_i32_impl node:$src)]>;
436 def AMDGPUffbh_u32 : PatFrags<(ops node:$src),
437 [(ctlz_zero_undef node:$src),
438 (AMDGPUffbh_u32_impl node:$src)]>;
440 def AMDGPUffbl_b32 : PatFrags<(ops node:$src),
441 [(cttz_zero_undef node:$src),
442 (AMDGPUffbl_b32_impl node:$src)]>;
444 def AMDGPUpkrtz_f16_f32 : PatFrags<(ops node:$src0, node:$src1),
445 [(int_amdgcn_cvt_pkrtz node:$src0, node:$src1),
446 (AMDGPUpkrtz_f16_f32_impl node:$src0, node:$src1)]>;
448 def AMDGPUpknorm_i16_f32 : PatFrags<(ops node:$src0, node:$src1),
449 [(int_amdgcn_cvt_pknorm_i16 node:$src0, node:$src1),
450 (AMDGPUpknorm_i16_f32_impl node:$src0, node:$src1)]>;
452 def AMDGPUpknorm_u16_f32 : PatFrags<(ops node:$src0, node:$src1),
453 [(int_amdgcn_cvt_pknorm_u16 node:$src0, node:$src1),
454 (AMDGPUpknorm_u16_f32_impl node:$src0, node:$src1)]>;
456 def AMDGPUpk_i16_i32 : PatFrags<(ops node:$src0, node:$src1),
457 [(int_amdgcn_cvt_pk_i16 node:$src0, node:$src1),
458 (AMDGPUpk_i16_i32_impl node:$src0, node:$src1)]>;
460 def AMDGPUpk_u16_u32 : PatFrags<(ops node:$src0, node:$src1),
461 [(int_amdgcn_cvt_pk_u16 node:$src0, node:$src1),
462 (AMDGPUpk_u16_u32_impl node:$src0, node:$src1)]>;
464 def AMDGPUfmad_ftz : PatFrags<(ops node:$src0, node:$src1, node:$src2),
465 [(int_amdgcn_fmad_ftz node:$src0, node:$src1, node:$src2),
466 (AMDGPUfmad_ftz_impl node:$src0, node:$src1, node:$src2)]>;
468 def AMDGPUmul_u24 : PatFrags<(ops node:$src0, node:$src1),
469 [(int_amdgcn_mul_u24 node:$src0, node:$src1),
470 (AMDGPUmul_u24_impl node:$src0, node:$src1)]>;
472 def AMDGPUmul_i24 : PatFrags<(ops node:$src0, node:$src1),
473 [(int_amdgcn_mul_i24 node:$src0, node:$src1),
474 (AMDGPUmul_i24_impl node:$src0, node:$src1)]>;
476 def AMDGPUmulhi_u24 : PatFrags<(ops node:$src0, node:$src1),
477 [(int_amdgcn_mulhi_u24 node:$src0, node:$src1),
478 (AMDGPUmulhi_u24_impl node:$src0, node:$src1)]>;
480 def AMDGPUmulhi_i24 : PatFrags<(ops node:$src0, node:$src1),
481 [(int_amdgcn_mulhi_i24 node:$src0, node:$src1),
482 (AMDGPUmulhi_i24_impl node:$src0, node:$src1)]>;
484 def AMDGPUbfe_i32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
485 [(int_amdgcn_sbfe node:$src0, node:$src1, node:$src2),
486 (AMDGPUbfe_i32_impl node:$src0, node:$src1, node:$src2)]>;
488 def AMDGPUbfe_u32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
489 [(int_amdgcn_ubfe node:$src0, node:$src1, node:$src2),
490 (AMDGPUbfe_u32_impl node:$src0, node:$src1, node:$src2)]>;
492 def AMDGPUfmul_legacy : PatFrags<(ops node:$src0, node:$src1),
493 [(int_amdgcn_fmul_legacy node:$src0, node:$src1),
494 (AMDGPUfmul_legacy_impl node:$src0, node:$src1)]>;
496 def AMDGPUfdot2 : PatFrags<(ops node:$src0, node:$src1, node:$src2, node:$clamp),
497 [(int_amdgcn_fdot2 node:$src0, node:$src1, node:$src2, node:$clamp),
498 (AMDGPUfdot2_impl node:$src0, node:$src1, node:$src2, node:$clamp)]>;
500 def AMDGPUdiv_fmas : PatFrags<(ops node:$src0, node:$src1, node:$src2, node:$vcc),
501 [(int_amdgcn_div_fmas node:$src0, node:$src1, node:$src2, node:$vcc),
502 (AMDGPUdiv_fmas_impl node:$src0, node:$src1, node:$src2, node:$vcc)]>;
504 def AMDGPUperm : PatFrags<(ops node:$src0, node:$src1, node:$src2),
505 [(int_amdgcn_perm node:$src0, node:$src1, node:$src2),
506 (AMDGPUperm_impl node:$src0, node:$src1, node:$src2)]>;