Lines Matching refs:getNode
587 const auto Flags = Op.getNode()->getFlags(); in mayIgnoreSignedZero()
875 if (!allUsesHaveSourceMods(Op.getNode())) in getNegatedExpression()
887 return DAG.getNode(AMDGPUISD::RCP, SL, VT, NegSrc, Op->getFlags()); in getNegatedExpression()
1232 return DAG.getNode(AMDGPUISD::ENDPGM, DL, MVT::Other, Chain); in LowerReturn()
1264 for (SDNode *U : DAG.getEntryNode().getNode()->uses()) { in addTokenForArgument()
1281 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains); in addTokenForArgument()
1446 SDValue Trap = DAG.getNode(ISD::TRAP, DL, MVT::Other, DAG.getEntryNode()); in LowerGlobalAddress()
1447 SDValue OutputChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, in LowerGlobalAddress()
1481 SDValue NewIn = DAG.getNode(ISD::BITCAST, SL, NewEltVT, In); in LowerCONCAT_VECTORS()
1491 return DAG.getNode(ISD::BITCAST, SL, VT, BV); in LowerCONCAT_VECTORS()
1519 SDValue Tmp = DAG.getNode(ISD::BITCAST, SL, NewSrcVT, Op.getOperand(0)); in LowerEXTRACT_SUBVECTOR()
1527 return DAG.getNode(ISD::BITCAST, SL, VT, Tmp); in LowerEXTRACT_SUBVECTOR()
1576 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS); in combineFMinMaxLegacyImpl()
1577 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS); in combineFMinMaxLegacyImpl()
1595 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS); in combineFMinMaxLegacyImpl()
1596 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS); in combineFMinMaxLegacyImpl()
1601 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS); in combineFMinMaxLegacyImpl()
1602 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS); in combineFMinMaxLegacyImpl()
1613 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS); in combineFMinMaxLegacyImpl()
1614 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS); in combineFMinMaxLegacyImpl()
1653 return DAG.getNode(ISD::FNEG, DL, VT, Combined); in combineFMinMaxLegacy()
1665 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in split64BitValue()
1670 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in split64BitValue()
1671 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in split64BitValue()
1679 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in getLoHalf64()
1681 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in getLoHalf64()
1687 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in getHiHalf64()
1689 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in getHiHalf64()
1718 SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoVT, N, in splitVector()
1720 SDValue Hi = DAG.getNode( in splitVector()
1770 Join = DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad); in SplitVectorLoad()
1772 Join = DAG.getNode(ISD::INSERT_SUBVECTOR, SL, VT, DAG.getUNDEF(VT), LoLoad, in SplitVectorLoad()
1774 Join = DAG.getNode( in SplitVectorLoad()
1780 SDValue Ops[] = {Join, DAG.getNode(ISD::TokenFactor, SL, MVT::Other, in SplitVectorLoad()
1814 {DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, VT, WideLoad, in WidenOrSplitVectorLoad()
1858 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore); in SplitVectorStore()
1894 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS); in LowerDIVREM24()
1897 jq = DAG.getNode(ISD::SRA, DL, VT, jq, in LowerDIVREM24()
1901 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT)); in LowerDIVREM24()
1911 SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia); in LowerDIVREM24()
1914 SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib); in LowerDIVREM24()
1916 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT, in LowerDIVREM24()
1917 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb)); in LowerDIVREM24()
1920 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq); in LowerDIVREM24()
1923 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq); in LowerDIVREM24()
1938 SDValue fr = DAG.getNode(OpCode, DL, FltVT, fqneg, fb, fa); in LowerDIVREM24()
1941 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq); in LowerDIVREM24()
1944 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr); in LowerDIVREM24()
1947 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb); in LowerDIVREM24()
1955 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT)); in LowerDIVREM24()
1958 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq); in LowerDIVREM24()
1961 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS); in LowerDIVREM24()
1962 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem); in LowerDIVREM24()
1968 Div = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Div, InRegSize); in LowerDIVREM24()
1969 Rem = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Rem, InRegSize); in LowerDIVREM24()
1972 Div = DAG.getNode(ISD::AND, DL, VT, Div, TruncMask); in LowerDIVREM24()
1973 Rem = DAG.getNode(ISD::AND, DL, VT, Rem, TruncMask); in LowerDIVREM24()
2004 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerUDIVREM64()
2010 Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV)); in LowerUDIVREM64()
2011 Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM)); in LowerUDIVREM64()
2029 SDValue Cvt_Lo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Lo); in LowerUDIVREM64()
2030 SDValue Cvt_Hi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Hi); in LowerUDIVREM64()
2031 SDValue Mad1 = DAG.getNode(FMAD, DL, MVT::f32, Cvt_Hi, in LowerUDIVREM64()
2034 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, DL, MVT::f32, Mad1); in LowerUDIVREM64()
2035 SDValue Mul1 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Rcp, in LowerUDIVREM64()
2037 SDValue Mul2 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Mul1, in LowerUDIVREM64()
2039 SDValue Trunc = DAG.getNode(ISD::FTRUNC, DL, MVT::f32, Mul2); in LowerUDIVREM64()
2040 SDValue Mad2 = DAG.getNode(FMAD, DL, MVT::f32, Trunc, in LowerUDIVREM64()
2043 SDValue Rcp_Lo = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Mad2); in LowerUDIVREM64()
2044 SDValue Rcp_Hi = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Trunc); in LowerUDIVREM64()
2054 SDValue Neg_RHS = DAG.getNode(ISD::SUB, DL, VT, Zero64, RHS); in LowerUDIVREM64()
2055 SDValue Mullo1 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Rcp64); in LowerUDIVREM64()
2056 SDValue Mulhi1 = DAG.getNode(ISD::MULHU, DL, VT, Rcp64, Mullo1); in LowerUDIVREM64()
2060 SDValue Add1_Lo = DAG.getNode(ISD::UADDO_CARRY, DL, HalfCarryVT, Rcp_Lo, in LowerUDIVREM64()
2062 SDValue Add1_Hi = DAG.getNode(ISD::UADDO_CARRY, DL, HalfCarryVT, Rcp_Hi, in LowerUDIVREM64()
2068 SDValue Mullo2 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Add1); in LowerUDIVREM64()
2069 SDValue Mulhi2 = DAG.getNode(ISD::MULHU, DL, VT, Add1, Mullo2); in LowerUDIVREM64()
2073 SDValue Add2_Lo = DAG.getNode(ISD::UADDO_CARRY, DL, HalfCarryVT, Add1_Lo, in LowerUDIVREM64()
2075 SDValue Add2_Hi = DAG.getNode(ISD::UADDO_CARRY, DL, HalfCarryVT, Add1_Hi, in LowerUDIVREM64()
2080 SDValue Mulhi3 = DAG.getNode(ISD::MULHU, DL, VT, LHS, Add2); in LowerUDIVREM64()
2082 SDValue Mul3 = DAG.getNode(ISD::MUL, DL, VT, RHS, Mulhi3); in LowerUDIVREM64()
2086 SDValue Sub1_Lo = DAG.getNode(ISD::USUBO_CARRY, DL, HalfCarryVT, LHS_Lo, in LowerUDIVREM64()
2088 SDValue Sub1_Hi = DAG.getNode(ISD::USUBO_CARRY, DL, HalfCarryVT, LHS_Hi, in LowerUDIVREM64()
2090 SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi); in LowerUDIVREM64()
2106 SDValue Sub2_Lo = DAG.getNode(ISD::USUBO_CARRY, DL, HalfCarryVT, Sub1_Lo, in LowerUDIVREM64()
2108 SDValue Sub2_Mi = DAG.getNode(ISD::USUBO_CARRY, DL, HalfCarryVT, Sub1_Mi, in LowerUDIVREM64()
2110 SDValue Sub2_Hi = DAG.getNode(ISD::USUBO_CARRY, DL, HalfCarryVT, Sub2_Mi, in LowerUDIVREM64()
2115 SDValue Add3 = DAG.getNode(ISD::ADD, DL, VT, Mulhi3, One64); in LowerUDIVREM64()
2124 SDValue Add4 = DAG.getNode(ISD::ADD, DL, VT, Add3, One64); in LowerUDIVREM64()
2126 SDValue Sub3_Lo = DAG.getNode(ISD::USUBO_CARRY, DL, HalfCarryVT, Sub2_Lo, in LowerUDIVREM64()
2128 SDValue Sub3_Mi = DAG.getNode(ISD::USUBO_CARRY, DL, HalfCarryVT, Sub2_Mi, in LowerUDIVREM64()
2130 SDValue Sub3_Hi = DAG.getNode(ISD::USUBO_CARRY, DL, HalfCarryVT, Sub3_Mi, in LowerUDIVREM64()
2152 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo); in LowerUDIVREM64()
2153 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo); in LowerUDIVREM64()
2157 REM = DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM); in LowerUDIVREM64()
2168 SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS); in LowerUDIVREM64()
2169 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, One); in LowerUDIVREM64()
2170 HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit); in LowerUDIVREM64()
2173 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT)); in LowerUDIVREM64()
2175 REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit); in LowerUDIVREM64()
2180 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT); in LowerUDIVREM64()
2183 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS); in LowerUDIVREM64()
2188 DIV = DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV); in LowerUDIVREM64()
2216 SDValue Z = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Y); in LowerUDIVREM()
2219 SDValue NegY = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Y); in LowerUDIVREM()
2220 SDValue NegYZ = DAG.getNode(ISD::MUL, DL, VT, NegY, Z); in LowerUDIVREM()
2221 Z = DAG.getNode(ISD::ADD, DL, VT, Z, in LowerUDIVREM()
2222 DAG.getNode(ISD::MULHU, DL, VT, Z, NegYZ)); in LowerUDIVREM()
2225 SDValue Q = DAG.getNode(ISD::MULHU, DL, VT, X, Z); in LowerUDIVREM()
2227 DAG.getNode(ISD::SUB, DL, VT, X, DAG.getNode(ISD::MUL, DL, VT, Q, Y)); in LowerUDIVREM()
2233 Q = DAG.getNode(ISD::SELECT, DL, VT, Cond, in LowerUDIVREM()
2234 DAG.getNode(ISD::ADD, DL, VT, Q, One), Q); in LowerUDIVREM()
2235 R = DAG.getNode(ISD::SELECT, DL, VT, Cond, in LowerUDIVREM()
2236 DAG.getNode(ISD::SUB, DL, VT, R, Y), R); in LowerUDIVREM()
2240 Q = DAG.getNode(ISD::SELECT, DL, VT, Cond, in LowerUDIVREM()
2241 DAG.getNode(ISD::ADD, DL, VT, Q, One), Q); in LowerUDIVREM()
2242 R = DAG.getNode(ISD::SELECT, DL, VT, Cond, in LowerUDIVREM()
2243 DAG.getNode(ISD::SUB, DL, VT, R, Y), R); in LowerUDIVREM()
2270 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero); in LowerSDIVREM()
2271 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero); in LowerSDIVREM()
2272 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerSDIVREM()
2275 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)), in LowerSDIVREM()
2276 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1)) in LowerSDIVREM()
2283 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign); in LowerSDIVREM()
2286 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign); in LowerSDIVREM()
2287 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign); in LowerSDIVREM()
2289 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign); in LowerSDIVREM()
2290 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign); in LowerSDIVREM()
2292 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS); in LowerSDIVREM()
2295 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign); in LowerSDIVREM()
2296 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign); in LowerSDIVREM()
2298 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign); in LowerSDIVREM()
2299 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign); in LowerSDIVREM()
2316 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y, Flags); in LowerFREM()
2317 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, VT, Div, Flags); in LowerFREM()
2318 SDValue Neg = DAG.getNode(ISD::FNEG, SL, VT, Trunc, Flags); in LowerFREM()
2320 return DAG.getNode(ISD::FMA, SL, VT, Neg, Y, X, Flags); in LowerFREM()
2331 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFCEIL()
2341 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc); in LowerFCEIL()
2343 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero); in LowerFCEIL()
2345 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFCEIL()
2353 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32, in extractF64Exponent()
2357 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart, in extractF64Exponent()
2381 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask); in LowerFTRUNC()
2385 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64); in LowerFTRUNC()
2387 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src); in LowerFTRUNC()
2391 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp); in LowerFTRUNC()
2393 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not); in LowerFTRUNC()
2403 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0); in LowerFTRUNC()
2404 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1); in LowerFTRUNC()
2406 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2); in LowerFTRUNC()
2418 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src); in LowerFROUNDEVEN()
2422 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign); in LowerFROUNDEVEN()
2423 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); in LowerFROUNDEVEN()
2425 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src); in LowerFROUNDEVEN()
2442 return DAG.getNode(ISD::FROUNDEVEN, SDLoc(Op), Op.getValueType(), in LowerFNEARBYINT()
2449 return DAG.getNode(ISD::FROUNDEVEN, SDLoc(Op), VT, Arg); in LowerFRINT()
2462 SDValue T = DAG.getNode(ISD::FTRUNC, SL, VT, X); in LowerFROUND()
2466 SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T); in LowerFROUND()
2468 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, VT, Diff); in LowerFROUND()
2478 SDValue OneOrZeroFP = DAG.getNode(ISD::SELECT, SL, VT, Cmp, One, Zero); in LowerFROUND()
2480 SDValue SignedOffset = DAG.getNode(ISD::FCOPYSIGN, SL, VT, OneOrZeroFP, X); in LowerFROUND()
2481 return DAG.getNode(ISD::FADD, SL, VT, T, SignedOffset); in LowerFROUND()
2492 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFFLOOR()
2502 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc); in LowerFFLOOR()
2504 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero); in LowerFFLOOR()
2506 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFFLOOR()
2575 SDValue Fabs = DAG.getNode(ISD::FABS, SL, VT, Src, Flags); in getIsFinite()
2602 DAG.getNode(ISD::SELECT, SL, VT, IsLtSmallestNormal, Scale32, One, Flags); in getScaledLogInput()
2604 SDValue ScaledInput = DAG.getNode(ISD::FMUL, SL, VT, Src, ScaleFactor, Flags); in getScaledLogInput()
2623 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src, Flags); in LowerFLOG2()
2624 SDValue Log = DAG.getNode(AMDGPUISD::LOG, SL, MVT::f32, Ext, Flags); in LowerFLOG2()
2625 return DAG.getNode(ISD::FP_ROUND, SL, VT, Log, in LowerFLOG2()
2632 return DAG.getNode(AMDGPUISD::LOG, SL, VT, Src, Flags); in LowerFLOG2()
2634 SDValue Log2 = DAG.getNode(AMDGPUISD::LOG, SL, VT, ScaledInput, Flags); in LowerFLOG2()
2639 DAG.getNode(ISD::SELECT, SL, VT, IsLtSmallestNormal, ThirtyTwo, Zero); in LowerFLOG2()
2640 return DAG.getNode(ISD::FSUB, SL, VT, Log2, ResultOffset, Flags); in LowerFLOG2()
2645 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, X, Y, Flags); in getMad()
2646 return DAG.getNode(ISD::FADD, SL, VT, Mul, C, Flags); in getMad()
2665 X = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, X, Flags); in LowerFLOGCommon()
2670 return DAG.getNode(ISD::FP_ROUND, DL, VT, Lowered, in LowerFLOGCommon()
2681 SDValue Y = DAG.getNode(AMDGPUISD::LOG, DL, VT, X, Flags); in LowerFLOGCommon()
2696 R = DAG.getNode(ISD::FMUL, DL, VT, Y, C, Flags); in LowerFLOGCommon()
2697 SDValue NegR = DAG.getNode(ISD::FNEG, DL, VT, R, Flags); in LowerFLOGCommon()
2698 SDValue FMA0 = DAG.getNode(ISD::FMA, DL, VT, Y, C, NegR, Flags); in LowerFLOGCommon()
2699 SDValue FMA1 = DAG.getNode(ISD::FMA, DL, VT, Y, CC, FMA0, Flags); in LowerFLOGCommon()
2700 R = DAG.getNode(ISD::FADD, DL, VT, R, FMA1, Flags); in LowerFLOGCommon()
2713 SDValue YAsInt = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Y); in LowerFLOGCommon()
2715 SDValue YHInt = DAG.getNode(ISD::AND, DL, MVT::i32, YAsInt, MaskConst); in LowerFLOGCommon()
2716 SDValue YH = DAG.getNode(ISD::BITCAST, DL, MVT::f32, YHInt); in LowerFLOGCommon()
2717 SDValue YT = DAG.getNode(ISD::FSUB, DL, VT, Y, YH, Flags); in LowerFLOGCommon()
2719 SDValue YTCT = DAG.getNode(ISD::FMUL, DL, VT, YT, CT, Flags); in LowerFLOGCommon()
2731 R = DAG.getNode(ISD::SELECT, DL, VT, IsFinite, R, Y, Flags); in LowerFLOGCommon()
2739 DAG.getNode(ISD::SELECT, DL, VT, IsScaled, ShiftK, Zero, Flags); in LowerFLOGCommon()
2740 R = DAG.getNode(ISD::FSUB, DL, VT, R, Shift, Flags); in LowerFLOGCommon()
2765 SDValue LogSrc = DAG.getNode(AMDGPUISD::LOG, SL, VT, ScaledInput, Flags); in LowerFLOGUnsafe()
2771 SDValue ResultOffset = DAG.getNode(ISD::SELECT, SL, VT, IsScaled, in LowerFLOGUnsafe()
2777 return DAG.getNode(ISD::FMA, SL, VT, LogSrc, Log2Inv, ResultOffset, in LowerFLOGUnsafe()
2779 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, LogSrc, Log2Inv, Flags); in LowerFLOGUnsafe()
2780 return DAG.getNode(ISD::FADD, SL, VT, Mul, ResultOffset); in LowerFLOGUnsafe()
2784 SDValue Log2Operand = DAG.getNode(LogOp, SL, VT, Src, Flags); in LowerFLOGUnsafe()
2787 return DAG.getNode(ISD::FMUL, SL, VT, Log2Operand, Log2BaseInvertedOperand, in LowerFLOGUnsafe()
2803 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src, Flags); in lowerFEXP2()
2804 SDValue Log = DAG.getNode(AMDGPUISD::EXP, SL, MVT::f32, Ext, Flags); in lowerFEXP2()
2805 return DAG.getNode(ISD::FP_ROUND, SL, VT, Log, in lowerFEXP2()
2812 return DAG.getNode(AMDGPUISD::EXP, SL, MVT::f32, Src, Flags); in lowerFEXP2()
2829 DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, SixtyFour, Zero); in lowerFEXP2()
2831 SDValue AddInput = DAG.getNode(ISD::FADD, SL, VT, Src, AddOffset, Flags); in lowerFEXP2()
2832 SDValue Exp2 = DAG.getNode(AMDGPUISD::EXP, SL, VT, AddInput, Flags); in lowerFEXP2()
2837 DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, TwoExpNeg64, One); in lowerFEXP2()
2839 return DAG.getNode(ISD::FMUL, SL, VT, Exp2, ResultScale, Flags); in lowerFEXP2()
2850 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, X, Log2E, Flags); in lowerFEXPUnsafe()
2851 return DAG.getNode(VT == MVT::f32 ? (unsigned)AMDGPUISD::EXP in lowerFEXPUnsafe()
2863 SDValue ScaledX = DAG.getNode(ISD::FADD, SL, VT, X, ScaleOffset, Flags); in lowerFEXPUnsafe()
2866 DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, ScaledX, X); in lowerFEXPUnsafe()
2868 SDValue ExpInput = DAG.getNode(ISD::FMUL, SL, VT, AdjustedX, Log2E, Flags); in lowerFEXPUnsafe()
2870 SDValue Exp2 = DAG.getNode(AMDGPUISD::EXP, SL, VT, ExpInput, Flags); in lowerFEXPUnsafe()
2874 DAG.getNode(ISD::FMUL, SL, VT, Exp2, ResultScaleFactor, Flags); in lowerFEXPUnsafe()
2876 return DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, AdjustedResult, Exp2, in lowerFEXPUnsafe()
2893 SDValue Mul0 = DAG.getNode(ISD::FMUL, SL, VT, X, K0, Flags); in lowerFEXP10Unsafe()
2894 SDValue Exp2_0 = DAG.getNode(Exp2Op, SL, VT, Mul0, Flags); in lowerFEXP10Unsafe()
2895 SDValue Mul1 = DAG.getNode(ISD::FMUL, SL, VT, X, K1, Flags); in lowerFEXP10Unsafe()
2896 SDValue Exp2_1 = DAG.getNode(Exp2Op, SL, VT, Mul1, Flags); in lowerFEXP10Unsafe()
2897 return DAG.getNode(ISD::FMUL, SL, VT, Exp2_0, Exp2_1); in lowerFEXP10Unsafe()
2912 SDValue ScaledX = DAG.getNode(ISD::FADD, SL, VT, X, ScaleOffset, Flags); in lowerFEXP10Unsafe()
2914 DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, ScaledX, X); in lowerFEXP10Unsafe()
2919 SDValue Mul0 = DAG.getNode(ISD::FMUL, SL, VT, AdjustedX, K0, Flags); in lowerFEXP10Unsafe()
2920 SDValue Exp2_0 = DAG.getNode(Exp2Op, SL, VT, Mul0, Flags); in lowerFEXP10Unsafe()
2921 SDValue Mul1 = DAG.getNode(ISD::FMUL, SL, VT, AdjustedX, K1, Flags); in lowerFEXP10Unsafe()
2922 SDValue Exp2_1 = DAG.getNode(Exp2Op, SL, VT, Mul1, Flags); in lowerFEXP10Unsafe()
2924 SDValue MulExps = DAG.getNode(ISD::FMUL, SL, VT, Exp2_0, Exp2_1, Flags); in lowerFEXP10Unsafe()
2928 DAG.getNode(ISD::FMUL, SL, VT, MulExps, ResultScaleFactor, Flags); in lowerFEXP10Unsafe()
2930 return DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, AdjustedResult, MulExps, in lowerFEXP10Unsafe()
2953 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, X, Flags); in lowerFEXP()
2955 return DAG.getNode(ISD::FP_ROUND, SL, VT, Lowered, in lowerFEXP()
3005 PH = DAG.getNode(ISD::FMUL, SL, VT, X, C, Flags); in lowerFEXP()
3006 SDValue NegPH = DAG.getNode(ISD::FNEG, SL, VT, PH, Flags); in lowerFEXP()
3007 SDValue FMA0 = DAG.getNode(ISD::FMA, SL, VT, X, C, NegPH, Flags); in lowerFEXP()
3008 PL = DAG.getNode(ISD::FMA, SL, VT, X, CC, FMA0, Flags); in lowerFEXP()
3019 SDValue XAsInt = DAG.getNode(ISD::BITCAST, SL, MVT::i32, X); in lowerFEXP()
3021 SDValue XHAsInt = DAG.getNode(ISD::AND, SL, MVT::i32, XAsInt, MaskConst); in lowerFEXP()
3022 SDValue XH = DAG.getNode(ISD::BITCAST, SL, VT, XHAsInt); in lowerFEXP()
3023 SDValue XL = DAG.getNode(ISD::FSUB, SL, VT, X, XH, Flags); in lowerFEXP()
3025 PH = DAG.getNode(ISD::FMUL, SL, VT, XH, CH, Flags); in lowerFEXP()
3027 SDValue XLCL = DAG.getNode(ISD::FMUL, SL, VT, XL, CL, Flags); in lowerFEXP()
3032 SDValue E = DAG.getNode(ISD::FROUNDEVEN, SL, VT, PH, Flags); in lowerFEXP()
3035 SDValue PHSubE = DAG.getNode(ISD::FSUB, SL, VT, PH, E, FlagsNoContract); in lowerFEXP()
3037 SDValue A = DAG.getNode(ISD::FADD, SL, VT, PHSubE, PL, Flags); in lowerFEXP()
3038 SDValue IntE = DAG.getNode(ISD::FP_TO_SINT, SL, MVT::i32, E); in lowerFEXP()
3039 SDValue Exp2 = DAG.getNode(AMDGPUISD::EXP, SL, VT, A, Flags); in lowerFEXP()
3041 SDValue R = DAG.getNode(ISD::FLDEXP, SL, VT, Exp2, IntE, Flags); in lowerFEXP()
3051 R = DAG.getNode(ISD::SELECT, SL, VT, Underflow, Zero, R); in lowerFEXP()
3061 R = DAG.getNode(ISD::SELECT, SL, VT, Overflow, Inf, R); in lowerFEXP()
3088 auto NewOp = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Arg); in lowerCTLZResults()
3090 NewOp = DAG.getNode(ISD::SHL, SL, MVT::i32, NewOp, ShiftVal); in lowerCTLZResults()
3091 NewOp = DAG.getNode(Op.getOpcode(), SL, MVT::i32, NewOp); in lowerCTLZResults()
3092 return DAG.getNode(ISD::TRUNCATE, SL, ResultVT, NewOp); in lowerCTLZResults()
3118 SDValue NewOpr = DAG.getNode(NewOpc, SL, MVT::i32, Src); in LowerCTLZ_CTTZ()
3122 NewOpr = DAG.getNode(ISD::UMIN, SL, MVT::i32, NewOpr, ConstVal); in LowerCTLZ_CTTZ()
3124 return DAG.getNode(ISD::ZERO_EXTEND, SL, Src.getValueType(), NewOpr); in LowerCTLZ_CTTZ()
3130 SDValue OprLo = DAG.getNode(NewOpc, SL, MVT::i32, Lo); in LowerCTLZ_CTTZ()
3131 SDValue OprHi = DAG.getNode(NewOpc, SL, MVT::i32, Hi); in LowerCTLZ_CTTZ()
3141 OprLo = DAG.getNode(AddOpc, SL, MVT::i32, OprLo, Const32); in LowerCTLZ_CTTZ()
3143 OprHi = DAG.getNode(AddOpc, SL, MVT::i32, OprHi, Const32); in LowerCTLZ_CTTZ()
3146 NewOpr = DAG.getNode(ISD::UMIN, SL, MVT::i32, OprLo, OprHi); in LowerCTLZ_CTTZ()
3149 NewOpr = DAG.getNode(ISD::UMIN, SL, MVT::i32, NewOpr, Const64); in LowerCTLZ_CTTZ()
3152 return DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i64, NewOpr); in LowerCTLZ_CTTZ()
3212 SDValue OppositeSign = DAG.getNode( in LowerINT_TO_FP32()
3213 ISD::SRA, SL, MVT::i32, DAG.getNode(ISD::XOR, SL, MVT::i32, Lo, Hi), in LowerINT_TO_FP32()
3216 DAG.getNode(ISD::ADD, SL, MVT::i32, DAG.getConstant(32, SL, MVT::i32), in LowerINT_TO_FP32()
3219 ShAmt = DAG.getNode(AMDGPUISD::FFBH_I32, SL, MVT::i32, Hi); in LowerINT_TO_FP32()
3222 ShAmt = DAG.getNode(ISD::SUB, SL, MVT::i32, ShAmt, in LowerINT_TO_FP32()
3224 ShAmt = DAG.getNode(ISD::UMIN, SL, MVT::i32, ShAmt, MaxShAmt); in LowerINT_TO_FP32()
3229 Sign = DAG.getNode(ISD::SRA, SL, MVT::i64, Src, in LowerINT_TO_FP32()
3232 DAG.getNode(ISD::XOR, SL, MVT::i64, in LowerINT_TO_FP32()
3233 DAG.getNode(ISD::ADD, SL, MVT::i64, Src, Sign), Sign); in LowerINT_TO_FP32()
3237 ShAmt = DAG.getNode(ISD::CTLZ, SL, MVT::i32, Hi); in LowerINT_TO_FP32()
3241 SDValue Norm = DAG.getNode(ISD::SHL, SL, MVT::i64, Src, ShAmt); in LowerINT_TO_FP32()
3246 SDValue Adjust = DAG.getNode(ISD::UMIN, SL, MVT::i32, in LowerINT_TO_FP32()
3249 Norm = DAG.getNode(ISD::OR, SL, MVT::i32, Hi, Adjust); in LowerINT_TO_FP32()
3253 SDValue FVal = DAG.getNode(Opc, SL, MVT::f32, Norm); in LowerINT_TO_FP32()
3257 ShAmt = DAG.getNode(ISD::SUB, SL, MVT::i32, DAG.getConstant(32, SL, MVT::i32), in LowerINT_TO_FP32()
3261 return DAG.getNode(ISD::FLDEXP, SL, MVT::f32, FVal, ShAmt); in LowerINT_TO_FP32()
3266 SDValue Exp = DAG.getNode(ISD::SHL, SL, MVT::i32, ShAmt, in LowerINT_TO_FP32()
3269 DAG.getNode(ISD::ADD, SL, MVT::i32, in LowerINT_TO_FP32()
3270 DAG.getNode(ISD::BITCAST, SL, MVT::i32, FVal), Exp); in LowerINT_TO_FP32()
3273 Sign = DAG.getNode(ISD::SHL, SL, MVT::i32, in LowerINT_TO_FP32()
3274 DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, Sign), in LowerINT_TO_FP32()
3276 IVal = DAG.getNode(ISD::OR, SL, MVT::i32, IVal, Sign); in LowerINT_TO_FP32()
3278 return DAG.getNode(ISD::BITCAST, SL, MVT::f32, IVal); in LowerINT_TO_FP32()
3289 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, in LowerINT_TO_FP64()
3292 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo); in LowerINT_TO_FP64()
3294 SDValue LdExp = DAG.getNode(ISD::FLDEXP, SL, MVT::f64, CvtHi, in LowerINT_TO_FP64()
3297 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo); in LowerINT_TO_FP64()
3313 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Src); in LowerUINT_TO_FP()
3314 return DAG.getNode(ISD::UINT_TO_FP, DL, DestVT, Ext); in LowerUINT_TO_FP()
3319 SDValue ToF32 = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f32, Src); in LowerUINT_TO_FP()
3321 return DAG.getNode(ISD::FP_ROUND, SL, MVT::bf16, ToF32, FPRoundFlag); in LowerUINT_TO_FP()
3330 SDValue IntToFp32 = DAG.getNode(Op.getOpcode(), DL, MVT::f32, Src); in LowerUINT_TO_FP()
3334 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerUINT_TO_FP()
3359 SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32, Src); in LowerSINT_TO_FP()
3360 return DAG.getNode(ISD::SINT_TO_FP, DL, DestVT, Ext); in LowerSINT_TO_FP()
3365 SDValue ToF32 = DAG.getNode(ISD::SINT_TO_FP, SL, MVT::f32, Src); in LowerSINT_TO_FP()
3367 return DAG.getNode(ISD::FP_ROUND, SL, MVT::bf16, ToF32, FPRoundFlag); in LowerSINT_TO_FP()
3379 SDValue IntToFp32 = DAG.getNode(Op.getOpcode(), DL, MVT::f32, Src); in LowerSINT_TO_FP()
3383 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerSINT_TO_FP()
3413 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, SrcVT, Src); in LowerFP_TO_INT64()
3421 Sign = DAG.getNode(ISD::SRA, SL, MVT::i32, in LowerFP_TO_INT64()
3422 DAG.getNode(ISD::BITCAST, SL, MVT::i32, Trunc), in LowerFP_TO_INT64()
3424 Trunc = DAG.getNode(ISD::FABS, SL, SrcVT, Trunc); in LowerFP_TO_INT64()
3442 SDValue Mul = DAG.getNode(ISD::FMUL, SL, SrcVT, Trunc, K0); in LowerFP_TO_INT64()
3444 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, SrcVT, Mul); in LowerFP_TO_INT64()
3446 SDValue Fma = DAG.getNode(ISD::FMA, SL, SrcVT, FloorMul, K1, Trunc); in LowerFP_TO_INT64()
3448 SDValue Hi = DAG.getNode((Signed && SrcVT == MVT::f64) ? ISD::FP_TO_SINT in LowerFP_TO_INT64()
3451 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma); in LowerFP_TO_INT64()
3453 SDValue Result = DAG.getNode(ISD::BITCAST, SL, MVT::i64, in LowerFP_TO_INT64()
3459 Sign = DAG.getNode(ISD::BITCAST, SL, MVT::i64, in LowerFP_TO_INT64()
3463 DAG.getNode(ISD::SUB, SL, MVT::i64, in LowerFP_TO_INT64()
3464 DAG.getNode(ISD::XOR, SL, MVT::i64, Result, Sign), Sign); in LowerFP_TO_INT64()
3476 return DAG.getNode(AMDGPUISD::FP_TO_FP16, DL, Op.getValueType(), N0); in LowerFP_TO_FP16()
3491 SDValue U = DAG.getNode(ISD::BITCAST, DL, MVT::i64, N0); in LowerFP_TO_FP16()
3492 SDValue UH = DAG.getNode(ISD::SRL, DL, MVT::i64, U, in LowerFP_TO_FP16()
3496 SDValue E = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerFP_TO_FP16()
3498 E = DAG.getNode(ISD::AND, DL, MVT::i32, E, in LowerFP_TO_FP16()
3502 E = DAG.getNode(ISD::ADD, DL, MVT::i32, E, in LowerFP_TO_FP16()
3505 SDValue M = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerFP_TO_FP16()
3507 M = DAG.getNode(ISD::AND, DL, MVT::i32, M, in LowerFP_TO_FP16()
3510 SDValue MaskedSig = DAG.getNode(ISD::AND, DL, MVT::i32, UH, in LowerFP_TO_FP16()
3512 MaskedSig = DAG.getNode(ISD::OR, DL, MVT::i32, MaskedSig, U); in LowerFP_TO_FP16()
3515 M = DAG.getNode(ISD::OR, DL, MVT::i32, M, Lo40Set); in LowerFP_TO_FP16()
3518 SDValue I = DAG.getNode(ISD::OR, DL, MVT::i32, in LowerFP_TO_FP16()
3523 SDValue N = DAG.getNode(ISD::OR, DL, MVT::i32, M, in LowerFP_TO_FP16()
3524 DAG.getNode(ISD::SHL, DL, MVT::i32, E, in LowerFP_TO_FP16()
3528 SDValue OneSubExp = DAG.getNode(ISD::SUB, DL, MVT::i32, in LowerFP_TO_FP16()
3530 SDValue B = DAG.getNode(ISD::SMAX, DL, MVT::i32, OneSubExp, Zero); in LowerFP_TO_FP16()
3531 B = DAG.getNode(ISD::SMIN, DL, MVT::i32, B, in LowerFP_TO_FP16()
3534 SDValue SigSetHigh = DAG.getNode(ISD::OR, DL, MVT::i32, M, in LowerFP_TO_FP16()
3537 SDValue D = DAG.getNode(ISD::SRL, DL, MVT::i32, SigSetHigh, B); in LowerFP_TO_FP16()
3538 SDValue D0 = DAG.getNode(ISD::SHL, DL, MVT::i32, D, B); in LowerFP_TO_FP16()
3540 D = DAG.getNode(ISD::OR, DL, MVT::i32, D, D1); in LowerFP_TO_FP16()
3543 SDValue VLow3 = DAG.getNode(ISD::AND, DL, MVT::i32, V, in LowerFP_TO_FP16()
3545 V = DAG.getNode(ISD::SRL, DL, MVT::i32, V, in LowerFP_TO_FP16()
3551 V1 = DAG.getNode(ISD::OR, DL, MVT::i32, V0, V1); in LowerFP_TO_FP16()
3552 V = DAG.getNode(ISD::ADD, DL, MVT::i32, V, V1); in LowerFP_TO_FP16()
3560 SDValue Sign = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerFP_TO_FP16()
3562 Sign = DAG.getNode(ISD::AND, DL, MVT::i32, Sign, in LowerFP_TO_FP16()
3565 V = DAG.getNode(ISD::OR, DL, MVT::i32, Sign, V); in LowerFP_TO_FP16()
3582 SDValue PromotedSrc = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src); in LowerFP_TO_INT()
3583 return DAG.getNode(Op.getOpcode(), DL, DestVT, PromotedSrc); in LowerFP_TO_INT()
3590 SDValue FpToInt32 = DAG.getNode(OpOpcode, DL, MVT::i32, Src); in LowerFP_TO_INT()
3591 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, FpToInt32); in LowerFP_TO_INT()
3601 SDValue FpToInt32 = DAG.getNode(OpOpcode, DL, MVT::i32, Src); in LowerFP_TO_INT()
3604 return DAG.getNode(Ext, DL, MVT::i64, FpToInt32); in LowerFP_TO_INT()
3631 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp); in LowerSIGN_EXTEND_INREG()
3688 return DAG.getNode(NewOpcode, SDLoc(Node24), Node24->getVTList(), in simplifyMul24()
3792 SDValue BC = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad); in performLoadCombine()
3843 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NewVT, Val); in performStoreCombine()
3845 SDValue CastBack = DAG.getNode(ISD::BITCAST, SL, VT, CastVal); in performStoreCombine()
3871 SDValue NewInReg = DAG.getNode(N->getOpcode(), SL, SrcVT, Src, N1); in performAssertSZExtCombine()
3872 return DAG.getNode(ISD::TRUNCATE, SL, N->getValueType(0), NewInReg); in performAssertSZExtCombine()
3926 SDValue LoAnd = DAG.getNode(Opc, SL, MVT::i32, Lo, LoRHS); in splitBinaryBitConstantOpImpl()
3927 SDValue HiAnd = DAG.getNode(Opc, SL, MVT::i32, Hi, HiRHS); in splitBinaryBitConstantOpImpl()
3931 DCI.AddToWorklist(Lo.getNode()); in splitBinaryBitConstantOpImpl()
3932 DCI.AddToWorklist(Hi.getNode()); in splitBinaryBitConstantOpImpl()
3935 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec); in splitBinaryBitConstantOpImpl()
3968 return DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec); in performShlCombine()
3979 SDValue Shl = DAG.getNode(ISD::SHL, SL, XVT, X, SDValue(RHS, 0)); in performShlCombine()
3997 SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS); in performShlCombine()
3998 SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, ShiftAmt); in performShlCombine()
4003 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec); in performShlCombine()
4022 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine()
4026 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec); in performSraCombine()
4032 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine()
4035 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec); in performSraCombine()
4060 return DAG.getNode( in performSrlCombine()
4062 DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(0), N->getOperand(1)), in performSrlCombine()
4063 DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(1), N->getOperand(1))); in performSrlCombine()
4082 SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst); in performSrlCombine()
4086 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildPair); in performSrlCombine()
4104 Elt0 = DAG.getNode(ISD::BITCAST, SL, in performTruncateCombine()
4108 return DAG.getNode(ISD::TRUNCATE, SL, VT, Elt0); in performTruncateCombine()
4125 SrcElt = DAG.getNode(ISD::BITCAST, SL, in performTruncateCombine()
4129 return DAG.getNode(ISD::TRUNCATE, SL, VT, SrcElt); in performTruncateCombine()
4160 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MidVT, in performTruncateCombine()
4162 DCI.AddToWorklist(Trunc.getNode()); in performTruncateCombine()
4166 DCI.AddToWorklist(Amt.getNode()); in performTruncateCombine()
4169 SDValue ShrunkShift = DAG.getNode(Src.getOpcode(), SL, MidVT, in performTruncateCombine()
4171 return DAG.getNode(ISD::TRUNCATE, SL, VT, ShrunkShift); in performTruncateCombine()
4187 return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1); in getMul24()
4193 SDValue MulLo = DAG.getNode(MulLoOpc, SL, MVT::i32, N0, N1); in getMul24()
4194 SDValue MulHi = DAG.getNode(MulHiOpc, SL, MVT::i32, N0, N1); in getMul24()
4196 return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64, MulLo, MulHi); in getMul24()
4234 SDValue AddOp = getAddOneOp(V.getNode()); in performMulCombine()
4249 SDValue MulVal = DAG.getNode(N->getOpcode(), DL, VT, N1, MulOper); in performMulCombine()
4250 return DAG.getNode(ISD::ADD, DL, VT, MulVal, N1); in performMulCombine()
4254 SDValue MulVal = DAG.getNode(N->getOpcode(), DL, VT, N0, MulOper); in performMulCombine()
4255 return DAG.getNode(ISD::ADD, DL, VT, MulVal, N0); in performMulCombine()
4333 SDValue Lo = DAG.getNode(LoOpcode, DL, MVT::i32, N0, N1); in performMulLoHiCombine()
4334 SDValue Hi = DAG.getNode(HiOpcode, DL, MVT::i32, N0, N1); in performMulLoHiCombine()
4367 SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_I24, DL, MVT::i32, N0, N1); in performMulhsCombine()
4368 DCI.AddToWorklist(Mulhi.getNode()); in performMulhsCombine()
4400 SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_U24, DL, MVT::i32, N0, N1); in performMulhuCombine()
4401 DCI.AddToWorklist(Mulhi.getNode()); in performMulhuCombine()
4416 Op = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Op); in getFFBX_U32()
4418 SDValue FFBX = DAG.getNode(Opc, DL, MVT::i32, Op); in getFFBX_U32()
4420 FFBX = DAG.getNode(ISD::TRUNCATE, DL, VT, FFBX); in getFFBX_U32()
4475 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT, Cond, in distributeOpThroughSelect()
4477 DCI.AddToWorklist(NewSelect.getNode()); in distributeOpThroughSelect()
4478 return DAG.getNode(Op, SL, VT, NewSelect); in distributeOpThroughSelect()
4499 if (!AMDGPUTargetLowering::allUsesHaveSourceMods(N.getNode())) in foldFreeOpFromSelect()
4515 !selectSupportsSourceMods(N.getNode())) { in foldFreeOpFromSelect()
4527 if (LHS.getOpcode() == ISD::FNEG && fnegFoldsIntoOp(NewLHS.getNode())) in foldFreeOpFromSelect()
4547 if (!AMDGPUTargetLowering::allUsesHaveSourceMods(N.getNode())) in foldFreeOpFromSelect()
4551 NewRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in foldFreeOpFromSelect()
4556 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT, in foldFreeOpFromSelect()
4558 DCI.AddToWorklist(NewSelect.getNode()); in foldFreeOpFromSelect()
4559 return DAG.getNode(LHS.getOpcode(), SL, VT, NewSelect); in foldFreeOpFromSelect()
4596 return DAG.getNode(ISD::SELECT, SL, VT, NewCond, False, True); in performSelectCombine()
4683 if (fnegFoldsIntoOp(N0.getNode()) && in shouldFoldFNegIntoSrc()
4684 (allUsesHaveSourceMods(N) || !allUsesHaveSourceMods(N0.getNode()))) in shouldFoldFNegIntoSrc()
4713 LHS = DAG.getNode(ISD::FNEG, SL, VT, LHS); in performFNegCombine()
4718 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
4722 SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS, N0->getFlags()); in performFNegCombine()
4726 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
4741 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
4743 SDValue Res = DAG.getNode(Opc, SL, VT, LHS, RHS, N0->getFlags()); in performFNegCombine()
4747 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
4766 MHS = DAG.getNode(ISD::FNEG, SL, VT, MHS); in performFNegCombine()
4769 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
4773 SDValue Res = DAG.getNode(Opc, SL, VT, LHS, MHS, RHS); in performFNegCombine()
4777 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
4801 SDValue NegLHS = DAG.getNode(ISD::FNEG, SL, VT, LHS); in performFNegCombine()
4802 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
4805 SDValue Res = DAG.getNode(Opposite, SL, VT, NegLHS, NegRHS, N0->getFlags()); in performFNegCombine()
4809 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
4815 Ops[I] = DAG.getNode(ISD::FNEG, SL, VT, N0->getOperand(I), N0->getFlags()); in performFNegCombine()
4817 SDValue Res = DAG.getNode(AMDGPUISD::FMED3, SL, VT, Ops, N0->getFlags()); in performFNegCombine()
4822 SDValue Neg = DAG.getNode(ISD::FNEG, SL, VT, Res); in performFNegCombine()
4846 return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0)); in performFNegCombine()
4854 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
4855 return DAG.getNode(Opc, SL, VT, Neg, N0->getFlags()); in performFNegCombine()
4862 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
4870 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
4871 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1)); in performFNegCombine()
4883 SDValue IntFNeg = DAG.getNode(ISD::XOR, SL, SrcVT, Src, in performFNegCombine()
4885 return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFNeg); in performFNegCombine()
4898 !fnegFoldsIntoOp(HighBits.getNode())) in performFNegCombine()
4910 SDValue CastHi = DAG.getNode(ISD::BITCAST, SL, MVT::f32, HighBits); in performFNegCombine()
4911 SDValue NegHi = DAG.getNode(ISD::FNEG, SL, MVT::f32, CastHi); in performFNegCombine()
4913 DAG.getNode(ISD::BITCAST, SL, HighBits.getValueType(), NegHi); in performFNegCombine()
4917 DCI.AddToWorklist(NegHi.getNode()); in performFNegCombine()
4919 DAG.getNode(ISD::BUILD_VECTOR, SL, BCSrc.getValueType(), Ops); in performFNegCombine()
4920 SDValue Result = DAG.getNode(ISD::BITCAST, SL, VT, Build); in performFNegCombine()
4923 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Result)); in performFNegCombine()
4935 DAG.getNode(ISD::BITCAST, SL, MVT::f32, BCSrc.getOperand(1)); in performFNegCombine()
4937 DAG.getNode(ISD::BITCAST, SL, MVT::f32, BCSrc.getOperand(2)); in performFNegCombine()
4939 SDValue NegLHS = DAG.getNode(ISD::FNEG, SL, MVT::f32, LHS); in performFNegCombine()
4940 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, MVT::f32, RHS); in performFNegCombine()
4942 return DAG.getNode(ISD::SELECT, SL, MVT::f32, BCSrc.getOperand(0), NegLHS, in performFNegCombine()
4969 SDValue IntFAbs = DAG.getNode(ISD::AND, SL, SrcVT, Src, in performFAbsCombine()
4971 return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFAbs); in performFAbsCombine()
5021 CastedElts.push_back(DAG.getNode(ISD::BITCAST, DL, DestEltVT, Elt)); in PerformDAGCombine()
5040 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, in PerformDAGCombine()
5043 return DAG.getNode(ISD::BITCAST, SL, DestVT, BV); in PerformDAGCombine()
5050 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, in PerformDAGCombine()
5054 return DAG.getNode(ISD::BITCAST, SL, DestVT, Vec); in PerformDAGCombine()
5140 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom, in PerformDAGCombine()
5166 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32, in PerformDAGCombine()
5302 Ptr = DAG.getNode(ISD::ADD, SL, MVT::i32, SP, Ptr); in storeStackInputValue()
5323 V = DAG.getNode(ISD::SRL, SL, VT, V, in loadInputValue()
5325 return DAG.getNode(ISD::AND, SL, VT, V, in loadInputValue()
5529 return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand); in getSqrtEstimate()
5550 return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand); in getRecipEstimate()
5689 auto GA = cast<GlobalAddressSDNode>(Op.getOperand(0).getNode()); in computeKnownBitsForTargetNode()