40 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {  in getEquivalentMemType()
49 unsigned AMDGPUTargetLowering::numBitsUnsigned(SDValue Op, SelectionDAG &DAG) {  in numBitsUnsigned()
53 unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) {  in numBitsSigned()
59 AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,  in AMDGPUTargetLowering()  function in AMDGPUTargetLowering
583 bool AMDGPUTargetLowering::mayIgnoreSignedZero(SDValue Op) const {  in mayIgnoreSignedZero()
710 bool AMDGPUTargetLowering::allUsesHaveSourceMods(const SDNode *N,  in allUsesHaveSourceMods()
736 EVT AMDGPUTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,  in getTypeForExtReturn()
747 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {  in getVectorIdxTy()
751 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {  in isSelectSupported()
757 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,  in isFPImmLegal()
765 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {  in ShouldShrinkFPConstant()
770 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,  in shouldReduceLoadWidth()
810 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy, EVT CastTy,  in isLoadBitCastBeneficial()
834 bool AMDGPUTargetLowering::isCheapToSpeculateCttz(Type *Ty) const {  in isCheapToSpeculateCttz()
838 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz(Type *Ty) const {  in isCheapToSpeculateCtlz()
842 bool AMDGPUTargetLowering::isSDNodeAlwaysUniform(const SDNode *N) const {  in isSDNodeAlwaysUniform()
867 SDValue AMDGPUTargetLowering::getNegatedExpression(  in getNegatedExpression()
902 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {  in isFAbsFree()
910 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {  in isFNegFree()
917 bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT,  in storeOfVectorConstantIsCheap()
923 bool AMDGPUTargetLowering::aggressivelyPreferBuildVectorSources(EVT VecVT) const {  in aggressivelyPreferBuildVectorSources()
935 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {  in isTruncateFree()
944 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {  in isTruncateFree()
956 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {  in isZExtFree()
966 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {  in isZExtFree()
978 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {  in isNarrowingProfitable()
988 bool AMDGPUTargetLowering::isDesirableToCommuteWithShift(  in isDesirableToCommuteWithShift()
1105 void AMDGPUTargetLowering::analyzeFormalArgumentsCompute(  in analyzeFormalArgumentsCompute()
1223 SDValue AMDGPUTargetLowering::LowerReturn(  in LowerReturn()
1240 CCAssignFn *AMDGPUTargetLowering::CCAssignFnForCall(CallingConv::ID CC,  in CCAssignFnForCall()
1245 CCAssignFn *AMDGPUTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,  in CCAssignFnForReturn()
1250 SDValue AMDGPUTargetLowering::addTokenForArgument(SDValue Chain,  in addTokenForArgument()
1284 SDValue AMDGPUTargetLowering::lowerUnhandledCall(CallLoweringInfo &CLI,  in lowerUnhandledCall()
1311 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,  in LowerCall()
1316 SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,  in LowerDYNAMIC_STACKALLOC()
1327 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,  in LowerOperation()
1375 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,  in ReplaceNodeResults()
1415 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,  in LowerGlobalAddress()
1466 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,  in LowerCONCAT_VECTORS()
1501 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,  in LowerEXTRACT_SUBVECTOR()
1554 SDValue AMDGPUTargetLowering::combineFMinMaxLegacyImpl(  in combineFMinMaxLegacyImpl()
1623 SDValue AMDGPUTargetLowering::combineFMinMaxLegacy(const SDLoc &DL, EVT VT,  in combineFMinMaxLegacy()
1662 AMDGPUTargetLowering::split64BitValue(SDValue Op, SelectionDAG &DAG) const {  in split64BitValue()
1676 SDValue AMDGPUTargetLowering::getLoHalf64(SDValue Op, SelectionDAG &DAG) const {  in getLoHalf64()
1684 SDValue AMDGPUTargetLowering::getHiHalf64(SDValue Op, SelectionDAG &DAG) const {  in getHiHalf64()
1696 AMDGPUTargetLowering::getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const {  in getSplitDestVTs()
1711 AMDGPUTargetLowering::splitVector(const SDValue &N, const SDLoc &DL,  in splitVector()
1726 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,  in SplitVectorLoad()
1786 SDValue AMDGPUTargetLowering::WidenOrSplitVectorLoad(SDValue Op,  in WidenOrSplitVectorLoad()
1820 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,  in SplitVectorStore()
1864 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG,  in LowerDIVREM24()
1979 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,  in LowerUDIVREM64()
2193 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,  in LowerUDIVREM()
2248 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,  in LowerSDIVREM()
2309 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {  in LowerFREM()
2323 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {  in LowerFCEIL()
2363 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {  in LowerFTRUNC()
2409 SDValue AMDGPUTargetLowering::LowerFROUNDEVEN(SDValue Op,  in LowerFROUNDEVEN()
2437 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op,  in LowerFNEARBYINT()
2446 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {  in LowerFRINT()
2457 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {  in LowerFROUND()
2484 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {  in LowerFFLOOR()
2533 bool AMDGPUTargetLowering::allowApproxFunc(const SelectionDAG &DAG,  in allowApproxFunc()
2541 bool AMDGPUTargetLowering::needsDenormHandlingF32(const SelectionDAG &DAG,  in needsDenormHandlingF32()
2550 SDValue AMDGPUTargetLowering::getIsLtSmallestNormal(SelectionDAG &DAG,  in getIsLtSmallestNormal()
2568 SDValue AMDGPUTargetLowering::getIsFinite(SelectionDAG &DAG, SDValue Src,  in getIsFinite()
2585 AMDGPUTargetLowering::getScaledLogInput(SelectionDAG &DAG, const SDLoc SL,  in getScaledLogInput()
2608 SDValue AMDGPUTargetLowering::LowerFLOG2(SDValue Op, SelectionDAG &DAG) const {  in LowerFLOG2()
2649 SDValue AMDGPUTargetLowering::LowerFLOGCommon(SDValue Op,  in LowerFLOGCommon()
2746 SDValue AMDGPUTargetLowering::LowerFLOG10(SDValue Op, SelectionDAG &DAG) const {  in LowerFLOG10()
2752 SDValue AMDGPUTargetLowering::LowerFLOGUnsafe(SDValue Src, const SDLoc &SL,  in LowerFLOGUnsafe()
2791 SDValue AMDGPUTargetLowering::lowerFEXP2(SDValue Op, SelectionDAG &DAG) const {  in lowerFEXP2()
2842 SDValue AMDGPUTargetLowering::lowerFEXPUnsafe(SDValue X, const SDLoc &SL,  in lowerFEXPUnsafe()
2882 SDValue AMDGPUTargetLowering::lowerFEXP10Unsafe(SDValue X, const SDLoc &SL,  in lowerFEXP10Unsafe()
2934 SDValue AMDGPUTargetLowering::lowerFEXP(SDValue Op, SelectionDAG &DAG) const {  in lowerFEXP()
3075 SDValue AMDGPUTargetLowering::lowerCTLZResults(SDValue Op,  in lowerCTLZResults()
3095 SDValue AMDGPUTargetLowering::LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const {  in LowerCTLZ_CTTZ()
3155 SDValue AMDGPUTargetLowering::LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG,  in LowerINT_TO_FP32()
3281 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,  in LowerINT_TO_FP64()
3300 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,  in LowerUINT_TO_FP()
3346 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,  in LowerSINT_TO_FP()
3395 SDValue AMDGPUTargetLowering::LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG,  in LowerFP_TO_INT64()
3470 SDValue AMDGPUTargetLowering::LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const {  in LowerFP_TO_FP16()
3569 SDValue AMDGPUTargetLowering::LowerFP_TO_INT(const SDValue Op,  in LowerFP_TO_INT()
3613 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,  in LowerSIGN_EXTEND_INREG()
3641   return AMDGPUTargetLowering::numBitsUnsigned(Op, DAG) <= 24;  in isU24()
3648          AMDGPUTargetLowering::numBitsSigned(Op, DAG) <= 24;  in isI24()
3725 bool AMDGPUTargetLowering::shouldCombineMemoryType(EVT VT) const {  in shouldCombineMemoryType()
3746 SDValue AMDGPUTargetLowering::performLoadCombine(SDNode *N,  in performLoadCombine()
3799 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,  in performStoreCombine()
3856 SDValue AMDGPUTargetLowering::performAssertSZExtCombine(SDNode *N,  in performAssertSZExtCombine()
3879 SDValue AMDGPUTargetLowering::performIntrinsicWOChainCombine(  in performIntrinsicWOChainCombine()
3915 SDValue AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(  in splitBinaryBitConstantOpImpl()
3938 SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,  in performShlCombine()
4006 SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,  in performSraCombine()
4041 SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N,  in performSrlCombine()
4089 SDValue AMDGPUTargetLowering::performTruncateCombine(  in performTruncateCombine()
4208 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,  in performMulCombine()
4296 AMDGPUTargetLowering::performMulLoHiCombine(SDNode *N,  in performMulLoHiCombine()
4339 SDValue AMDGPUTargetLowering::performMulhsCombine(SDNode *N,  in performMulhsCombine()
4372 SDValue AMDGPUTargetLowering::performMulhuCombine(SDNode *N,  in performMulhuCombine()
4405 SDValue AMDGPUTargetLowering::getFFBX_U32(SelectionDAG &DAG,  in getFFBX_U32()
4432 SDValue AMDGPUTargetLowering::performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond,  in performCtlz_CttzCombine()
4489 AMDGPUTargetLowering::foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI,  in foldFreeOpFromSelect()
4499     if (!AMDGPUTargetLowering::allUsesHaveSourceMods(N.getNode()))  in foldFreeOpFromSelect()
4547       if (!AMDGPUTargetLowering::allUsesHaveSourceMods(N.getNode()))  in foldFreeOpFromSelect()
4566 SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,  in performSelectCombine()
4625 AMDGPUTargetLowering::getConstantNegateCost(const ConstantFPSDNode *C) const {  in getConstantNegateCost()
4635 bool AMDGPUTargetLowering::isConstantCostlierToNegate(SDValue N) const {  in isConstantCostlierToNegate()
4641 bool AMDGPUTargetLowering::isConstantCheaperToNegate(SDValue N) const {  in isConstantCheaperToNegate()
4672 bool AMDGPUTargetLowering::shouldFoldFNegIntoSrc(SDNode *N, SDValue N0) {  in shouldFoldFNegIntoSrc()
4691 SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,  in performFNegCombine()
4953 SDValue AMDGPUTargetLowering::performFAbsCombine(SDNode *N,  in performFAbsCombine()
4978 SDValue AMDGPUTargetLowering::performRcpCombine(SDNode *N,  in performRcpCombine()
4990 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,  in PerformDAGCombine()
5237 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,  in CreateLiveInRegister()
5273 SDValue AMDGPUTargetLowering::loadStackInputValue(SelectionDAG &DAG,  in loadStackInputValue()
5289 SDValue AMDGPUTargetLowering::storeStackInputValue(SelectionDAG &DAG,  in storeStackInputValue()
5308 SDValue AMDGPUTargetLowering::loadInputValue(SelectionDAG &DAG,  in loadInputValue()
5329 uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(  in getImplicitParameterOffset()
5348 uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(  in getImplicitParameterOffset()
5356 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {  in getTargetNodeName()
5520 SDValue AMDGPUTargetLowering::getSqrtEstimate(SDValue Operand,  in getSqrtEstimate()
5538 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,  in getRecipEstimate()
5572 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(  in computeKnownBitsForTargetNode()
5737 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(  in ComputeNumSignBitsForTargetNode()
5798 unsigned AMDGPUTargetLowering::computeNumSignBitsForTargetInstr(  in computeNumSignBitsForTargetInstr()
5835 bool AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,  in isKnownNeverNaNForTargetNode()
5949 bool AMDGPUTargetLowering::isReassocProfitable(MachineRegisterInfo &MRI,  in isReassocProfitable()
5955 AMDGPUTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {  in shouldExpandAtomicRMWInIR()
5978 bool AMDGPUTargetLowering::shouldSinkOperands(  in shouldSinkOperands()