Lines Matching refs:k_Register
346 k_Register, enumerator
548 case k_Register: in AArch64Operand()
658 assert(Kind == k_Register && "Invalid access!"); in getReg()
683 assert(Kind == k_Register && "Invalid access!"); in getRegEqualityTy()
755 if (Kind == k_Register) in getShiftExtendType()
763 if (Kind == k_Register) in getShiftExtendAmount()
771 if (Kind == k_Register) in hasShiftExtendAmount()
1206 return Kind == k_Register; in isReg()
1212 return Kind == k_Register && Reg.Kind == RegKind::Scalar; in isScalarReg()
1216 return Kind == k_Register && Reg.Kind == RegKind::NeonVector; in isNeonVectorReg()
1220 return Kind == k_Register && Reg.Kind == RegKind::NeonVector && in isNeonVectorRegLo()
1228 return Kind == k_Register && Reg.Kind == RegKind::NeonVector && in isNeonVectorReg0to7()
1250 return (Kind == k_Register && Reg.Kind == RK) && in isSVEPredicateAsCounterReg()
1273 return (Kind == k_Register && Reg.Kind == RK) && in isSVEVectorReg()
1278 return Kind == k_Register && Reg.Kind == RegKind::Scalar && in isFPRasZPR()
1284 if (Kind != k_Register || Reg.Kind != RegKind::SVEPredicateVector) in isSVEPredicateVectorRegOfWidth()
1295 if (Kind != k_Register || Reg.Kind != RegKind::SVEPredicateAsCounter) in isSVEPredicateAsCounterRegOfWidth()
1306 if (Kind != k_Register || Reg.Kind != RegKind::SVEDataVector) in isSVEDataVectorRegOfWidth()
1339 return Kind == k_Register && Reg.Kind == RegKind::Scalar && in isGPR32as64()
1344 return Kind == k_Register && Reg.Kind == RegKind::Scalar && in isGPR64as32()
1349 return Kind == k_Register && Reg.Kind == RegKind::Scalar && in isGPR64x8()
1355 return Kind == k_Register && Reg.Kind == RegKind::Scalar && in isWSeqPair()
1361 return Kind == k_Register && Reg.Kind == RegKind::Scalar && in isXSeqPair()
1384 return Kind == k_Register && Reg.Kind == RegKind::Scalar && in isGPR64()
1390 if (Kind != k_Register || Reg.Kind != RegKind::Scalar) in isGPR64WithShiftExtend()
2239 auto Op = std::make_unique<AArch64Operand>(k_Register, Ctx); in CreateReg()
2585 case k_Register: in print()