Lines Matching refs:MF
71 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { in getCalleeSavedRegs()
72 assert(MF && "Invalid MachineFunction pointer."); in getCalleeSavedRegs()
74 if (MF->getFunction().getCallingConv() == CallingConv::GHC) in getCalleeSavedRegs()
78 if (MF->getFunction().getCallingConv() == CallingConv::AnyReg) in getCalleeSavedRegs()
81 if (MF->getFunction().getCallingConv() == CallingConv::ARM64EC_Thunk_X64) in getCalleeSavedRegs()
86 if (MF->getSubtarget<AArch64Subtarget>().isTargetDarwin()) in getCalleeSavedRegs()
87 return getDarwinCalleeSavedRegs(MF); in getCalleeSavedRegs()
89 if (MF->getFunction().getCallingConv() == CallingConv::CFGuard_Check) in getCalleeSavedRegs()
91 if (MF->getSubtarget<AArch64Subtarget>().isTargetWindows()) { in getCalleeSavedRegs()
92 if (MF->getSubtarget<AArch64Subtarget>().getTargetLowering() in getCalleeSavedRegs()
94 MF->getFunction().getAttributes().hasAttrSomewhere( in getCalleeSavedRegs()
97 if (MF->getFunction().getCallingConv() == CallingConv::SwiftTail) in getCalleeSavedRegs()
101 if (MF->getFunction().getCallingConv() == CallingConv::AArch64_VectorCall) in getCalleeSavedRegs()
103 if (MF->getFunction().getCallingConv() == CallingConv::AArch64_SVE_VectorCall) in getCalleeSavedRegs()
105 if (MF->getFunction().getCallingConv() == in getCalleeSavedRegs()
111 if (MF->getFunction().getCallingConv() == in getCalleeSavedRegs()
117 if (MF->getSubtarget<AArch64Subtarget>().getTargetLowering() in getCalleeSavedRegs()
119 MF->getFunction().getAttributes().hasAttrSomewhere( in getCalleeSavedRegs()
122 if (MF->getFunction().getCallingConv() == CallingConv::SwiftTail) in getCalleeSavedRegs()
124 if (MF->getFunction().getCallingConv() == CallingConv::PreserveMost) in getCalleeSavedRegs()
126 if (MF->getFunction().getCallingConv() == CallingConv::PreserveAll) in getCalleeSavedRegs()
128 if (MF->getFunction().getCallingConv() == CallingConv::Win64) in getCalleeSavedRegs()
132 if (MF->getInfo<AArch64FunctionInfo>()->isSVECC()) in getCalleeSavedRegs()
138 AArch64RegisterInfo::getDarwinCalleeSavedRegs(const MachineFunction *MF) const { in getDarwinCalleeSavedRegs()
139 assert(MF && "Invalid MachineFunction pointer."); in getDarwinCalleeSavedRegs()
140 assert(MF->getSubtarget<AArch64Subtarget>().isTargetDarwin() && in getDarwinCalleeSavedRegs()
143 if (MF->getFunction().getCallingConv() == CallingConv::CFGuard_Check) in getDarwinCalleeSavedRegs()
146 if (MF->getFunction().getCallingConv() == CallingConv::AArch64_VectorCall) in getDarwinCalleeSavedRegs()
148 if (MF->getFunction().getCallingConv() == CallingConv::AArch64_SVE_VectorCall) in getDarwinCalleeSavedRegs()
151 if (MF->getFunction().getCallingConv() == in getDarwinCalleeSavedRegs()
157 if (MF->getFunction().getCallingConv() == in getDarwinCalleeSavedRegs()
163 if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS) in getDarwinCalleeSavedRegs()
164 return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() in getDarwinCalleeSavedRegs()
167 if (MF->getSubtarget<AArch64Subtarget>().getTargetLowering() in getDarwinCalleeSavedRegs()
169 MF->getFunction().getAttributes().hasAttrSomewhere( in getDarwinCalleeSavedRegs()
172 if (MF->getFunction().getCallingConv() == CallingConv::SwiftTail) in getDarwinCalleeSavedRegs()
174 if (MF->getFunction().getCallingConv() == CallingConv::PreserveMost) in getDarwinCalleeSavedRegs()
176 if (MF->getFunction().getCallingConv() == CallingConv::PreserveAll) in getDarwinCalleeSavedRegs()
178 if (MF->getFunction().getCallingConv() == CallingConv::Win64) in getDarwinCalleeSavedRegs()
184 const MachineFunction *MF) const { in getCalleeSavedRegsViaCopy()
185 assert(MF && "Invalid MachineFunction pointer."); in getCalleeSavedRegsViaCopy()
186 if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && in getCalleeSavedRegsViaCopy()
187 MF->getInfo<AArch64FunctionInfo>()->isSplitCSR()) in getCalleeSavedRegsViaCopy()
193 MachineFunction &MF) const { in UpdateCustomCalleeSavedRegs()
194 const MCPhysReg *CSRs = getCalleeSavedRegs(&MF); in UpdateCustomCalleeSavedRegs()
200 if (MF.getSubtarget<AArch64Subtarget>().isXRegCustomCalleeSaved(i)) { in UpdateCustomCalleeSavedRegs()
206 MF.getRegInfo().setCalleeSavedRegs(UpdatedCSRs); in UpdateCustomCalleeSavedRegs()
223 AArch64RegisterInfo::getDarwinCallPreservedMask(const MachineFunction &MF, in getDarwinCallPreservedMask() argument
225 assert(MF.getSubtarget<AArch64Subtarget>().isTargetDarwin() && in getDarwinCallPreservedMask()
246 if (MF.getSubtarget<AArch64Subtarget>() in getDarwinCallPreservedMask()
249 MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError)) in getDarwinCallPreservedMask()
261 AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF, in getCallPreservedMask() argument
263 bool SCS = MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack); in getCallPreservedMask()
271 if (MF.getSubtarget<AArch64Subtarget>().isTargetDarwin()) { in getCallPreservedMask()
274 return getDarwinCallPreservedMask(MF, CC); in getCallPreservedMask()
288 if (MF.getSubtarget<AArch64Subtarget>().getTargetLowering() in getCallPreservedMask()
290 MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError)) in getCallPreservedMask()
310 const MachineFunction &MF) const { in getCustomEHPadPreservedMask()
311 if (MF.getSubtarget<AArch64Subtarget>().isTargetLinux()) in getCustomEHPadPreservedMask()
325 void AArch64RegisterInfo::UpdateCustomCallPreservedMask(MachineFunction &MF, in UpdateCustomCallPreservedMask() argument
327 uint32_t *UpdatedMask = MF.allocateRegMask(); in UpdateCustomCallPreservedMask()
332 if (MF.getSubtarget<AArch64Subtarget>().isXRegCustomCalleeSaved(i)) { in UpdateCustomCallPreservedMask()
358 AArch64RegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF, in getThisReturnPreservedMask() argument
368 if (MF.getSubtarget<AArch64Subtarget>().isTargetDarwin()) in getThisReturnPreservedMask()
378 AArch64RegisterInfo::explainReservedReg(const MachineFunction &MF, in explainReservedReg() argument
380 if (hasBasePointer(MF) && MCRegisterInfo::regsOverlap(PhysReg, AArch64::X19)) in explainReservedReg()
383 if (MF.getSubtarget<AArch64Subtarget>().isWindowsArm64EC()) { in explainReservedReg()
405 AArch64RegisterInfo::getStrictlyReservedRegs(const MachineFunction &MF) const { in getStrictlyReservedRegs()
406 const AArch64FrameLowering *TFI = getFrameLowering(MF); in getStrictlyReservedRegs()
413 if (TFI->hasFP(MF) || TT.isOSDarwin()) in getStrictlyReservedRegs()
416 if (MF.getSubtarget<AArch64Subtarget>().isWindowsArm64EC()) { in getStrictlyReservedRegs()
429 if (MF.getSubtarget<AArch64Subtarget>().isXRegisterReserved(i)) in getStrictlyReservedRegs()
433 if (hasBasePointer(MF)) in getStrictlyReservedRegs()
437 if (MF.getFunction().hasFnAttribute(Attribute::SpeculativeLoadHardening)) in getStrictlyReservedRegs()
441 if (MF.getSubtarget<AArch64Subtarget>().hasSME()) { in getStrictlyReservedRegs()
446 if (MF.getSubtarget<AArch64Subtarget>().hasSME2()) { in getStrictlyReservedRegs()
454 if (MF.getFunction().getCallingConv() == CallingConv::GRAAL) { in getStrictlyReservedRegs()
466 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const { in getReservedRegs()
467 BitVector Reserved = getStrictlyReservedRegs(MF); in getReservedRegs()
470 if (MF.getSubtarget<AArch64Subtarget>().isXRegisterReservedForRA(i)) in getReservedRegs()
478 bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF, in isReservedReg() argument
480 return getReservedRegs(MF)[Reg]; in isReservedReg()
483 bool AArch64RegisterInfo::isStrictlyReservedReg(const MachineFunction &MF, in isStrictlyReservedReg() argument
485 return getStrictlyReservedRegs(MF)[Reg]; in isStrictlyReservedReg()
488 bool AArch64RegisterInfo::isAnyArgRegReserved(const MachineFunction &MF) const { in isAnyArgRegReserved()
489 return llvm::any_of(*AArch64::GPR64argRegClass.MC, [this, &MF](MCPhysReg r) { in isAnyArgRegReserved()
490 return isStrictlyReservedReg(MF, r); in isAnyArgRegReserved()
495 const MachineFunction &MF) const { in emitReservedArgRegCallError()
496 const Function &F = MF.getFunction(); in emitReservedArgRegCallError()
501 bool AArch64RegisterInfo::isAsmClobberable(const MachineFunction &MF, in isAsmClobberable() argument
506 if (MF.getFunction().hasFnAttribute(Attribute::SpeculativeLoadHardening) && in isAsmClobberable()
514 return !isReservedReg(MF, PhysReg); in isAsmClobberable()
518 AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF, in getPointerRegClass() argument
532 bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const { in hasBasePointer()
533 const MachineFrameInfo &MFI = MF.getFrameInfo(); in hasBasePointer()
543 if (MFI.hasVarSizedObjects() || MF.hasEHFunclets()) { in hasBasePointer()
544 if (hasStackRealignment(MF)) in hasBasePointer()
547 if (MF.getSubtarget<AArch64Subtarget>().hasSVE()) { in hasBasePointer()
548 const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>(); in hasBasePointer()
568 bool AArch64RegisterInfo::isArgumentRegister(const MachineFunction &MF, in isArgumentRegister() argument
570 CallingConv::ID CC = MF.getFunction().getCallingConv(); in isArgumentRegister()
571 const AArch64Subtarget &STI = MF.getSubtarget<AArch64Subtarget>(); in isArgumentRegister()
572 bool IsVarArg = STI.isCallingConvWin64(MF.getFunction().getCallingConv()); in isArgumentRegister()
643 AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const { in getFrameRegister()
644 const AArch64FrameLowering *TFI = getFrameLowering(MF); in getFrameRegister()
645 return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP; in getFrameRegister()
649 const MachineFunction &MF) const { in requiresRegisterScavenging()
654 const MachineFunction &MF) const { in requiresVirtualBaseRegisters()
659 AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const { in useFPForScavengingIndex()
668 const AArch64FrameLowering &TFI = *getFrameLowering(MF); in useFPForScavengingIndex()
669 const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>(); in useFPForScavengingIndex()
670 assert((!MF.getSubtarget<AArch64Subtarget>().hasSVE() || in useFPForScavengingIndex()
673 return TFI.hasFP(MF) && !hasStackRealignment(MF) && !AFI->getStackSizeSVE(); in useFPForScavengingIndex()
677 const MachineFunction &MF) const { in requiresFrameIndexScavenging()
682 AArch64RegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const { in cannotEliminateFrame()
683 const MachineFrameInfo &MFI = MF.getFrameInfo(); in cannotEliminateFrame()
684 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI.adjustsStack()) in cannotEliminateFrame()
716 MachineFunction &MF = *MI->getParent()->getParent(); in needsFrameBaseReg() local
717 const AArch64FrameLowering *TFI = getFrameLowering(MF); in needsFrameBaseReg()
718 MachineFrameInfo &MFI = MF.getFrameInfo(); in needsFrameBaseReg()
738 if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset)) in needsFrameBaseReg()
775 const MachineFunction &MF = *MBB->getParent(); in materializeFrameBaseRegister() local
777 MF.getSubtarget<AArch64Subtarget>().getInstrInfo(); in materializeFrameBaseRegister()
781 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
803 const MachineFunction *MF = MI.getParent()->getParent(); in resolveFrameIndex() local
805 MF->getSubtarget<AArch64Subtarget>().getInstrInfo(); in resolveFrameIndex()
874 MachineFunction &MF = *MBB.getParent(); in eliminateFrameIndex() local
875 const MachineFrameInfo &MFI = MF.getFrameInfo(); in eliminateFrameIndex()
877 MF.getSubtarget<AArch64Subtarget>().getInstrInfo(); in eliminateFrameIndex()
878 const AArch64FrameLowering *TFI = getFrameLowering(MF); in eliminateFrameIndex()
889 TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg, in eliminateFrameIndex()
900 StackOffset Offset = TFI->getNonLocalFrameIndexReference(MF, FrameIndex); in eliminateFrameIndex()
910 const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>(); in eliminateFrameIndex()
923 MF, FrameIndex, FrameReg, /*PreferFP=*/false, /*ForSimm=*/true); in eliminateFrameIndex()
925 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass); in eliminateFrameIndex()
941 MF, FrameIndex, FrameReg, /*PreferFP=*/false, /*ForSimm=*/true); in eliminateFrameIndex()
961 MachineFunction &MF) const { in getRegPressureLimit()
962 const AArch64FrameLowering *TFI = getFrameLowering(MF); in getRegPressureLimit()
976 - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP in getRegPressureLimit()
977 - MF.getSubtarget<AArch64Subtarget>().getNumXRegisterReserved() in getRegPressureLimit()
978 - hasBasePointer(MF); // X19 in getRegPressureLimit()
1008 const MachineFunction &MF) const { in getLocalAddressRegister()
1009 const auto &MFI = MF.getFrameInfo(); in getLocalAddressRegister()
1010 if (!MF.hasEHFunclets() && !MFI.hasVarSizedObjects()) in getLocalAddressRegister()
1012 else if (hasStackRealignment(MF)) in getLocalAddressRegister()
1014 return getFrameRegister(MF); in getLocalAddressRegister()