831     bool isDef = any_of(I.operands(), [DefReg, TRI](MachineOperand &MOP) {  in forAllMIsUntilDef()  argument
832       return MOP.isReg() && MOP.isDef() && !MOP.isDebug() && MOP.getReg() &&  in forAllMIsUntilDef()
833              TRI->regsOverlap(MOP.getReg(), DefReg);  in forAllMIsUntilDef()
846   for (const MachineOperand &MOP : phys_regs_and_masks(MI))  in updateDefinedRegisters()  local
847     if (MOP.isReg() && MOP.isKill())  in updateDefinedRegisters()
848       Units.removeReg(MOP.getReg());  in updateDefinedRegisters()
850   for (const MachineOperand &MOP : phys_regs_and_masks(MI))  in updateDefinedRegisters()  local
851     if (MOP.isReg() && !MOP.isKill())  in updateDefinedRegisters()
852       Units.addReg(MOP.getReg());  in updateDefinedRegisters()
899               MachineOperand &MOP = MI.getOperand(OpIdx);  in mergePairedInsns()  local
902               if (MOP.isReg() && !MOP.isDebug() && MOP.getReg() &&  in mergePairedInsns()
904                    (MOP.isDef() && MOP.isImplicit())) &&  in mergePairedInsns()
905                   TRI->regsOverlap(MOP.getReg(), RegToRename)) {  in mergePairedInsns()
906                 assert((MOP.isImplicit() ||  in mergePairedInsns()
907                         (MOP.isRenamable() && !MOP.isEarlyClobber())) &&  in mergePairedInsns()
917                       TRI->getMinimalPhysRegClass(MOP.getReg()));  in mergePairedInsns()
919                 MOP.setReg(MatchingReg);  in mergePairedInsns()
925               MachineOperand &MOP = MI.getOperand(OpIdx);  in mergePairedInsns()  local
926               if (MOP.isReg() && !MOP.isDebug() && MOP.getReg() &&  in mergePairedInsns()
927                   TRI->regsOverlap(MOP.getReg(), RegToRename)) {  in mergePairedInsns()
928                 assert((MOP.isImplicit() ||  in mergePairedInsns()
929                         (MOP.isRenamable() && !MOP.isEarlyClobber())) &&  in mergePairedInsns()
937                       TRI->getMinimalPhysRegClass(MOP.getReg()));  in mergePairedInsns()
940                 MOP.setReg(MatchingReg);  in mergePairedInsns()
967                     [this, RegToCheck](const MachineOperand &MOP) {  in mergePairedInsns()  argument
968                       return !MOP.isReg() || MOP.isDebug() || !MOP.getReg() ||  in mergePairedInsns()
969                              MOP.isUndef() ||  in mergePairedInsns()
970                              !TRI->regsOverlap(MOP.getReg(), RegToCheck);  in mergePairedInsns()
1125     for (const MachineOperand &MOP : phys_regs_and_masks(*I))  in mergePairedInsns()  local
1126       if (MOP.isReg() && MOP.isKill())  in mergePairedInsns()
1127         DefinedInBB.addReg(MOP.getReg());  in mergePairedInsns()
1420 static bool canRenameMOP(const MachineOperand &MOP,  in canRenameMOP()  argument
1422   if (MOP.isReg()) {  in canRenameMOP()
1423     auto *RegClass = TRI->getMinimalPhysRegClass(MOP.getReg());  in canRenameMOP()
1434           << MOP << ")\n");  in canRenameMOP()
1441     if (MOP.isImplicit() && MOP.isDef()) {  in canRenameMOP()
1442       if (!isRewritableImplicitDef(MOP.getParent()->getOpcode()))  in canRenameMOP()
1445           MOP.getParent()->getOperand(0).getReg(), MOP.getReg());  in canRenameMOP()
1448   return MOP.isImplicit() ||  in canRenameMOP()
1449          (MOP.isRenamable() && !MOP.isEarlyClobber() && !MOP.isTied());  in canRenameMOP()
1466               [TRI, RegToRename](const MachineOperand &MOP) {  in canRenameUpToDef()  argument
1467                 return MOP.isReg() && !MOP.isDebug() && MOP.getReg() &&  in canRenameUpToDef()
1468                        MOP.isImplicit() && MOP.isKill() &&  in canRenameUpToDef()
1469                        TRI->regsOverlap(RegToRename, MOP.getReg());  in canRenameUpToDef()
1511       for (auto &MOP : MI.operands()) {  in canRenameUpToDef()  local
1512         if (!MOP.isReg() || !MOP.isDef() || MOP.isDebug() || !MOP.getReg() ||  in canRenameUpToDef()
1513             !TRI->regsOverlap(MOP.getReg(), RegToRename))  in canRenameUpToDef()
1515         if (!canRenameMOP(MOP, TRI)) {  in canRenameUpToDef()
1516           LLVM_DEBUG(dbgs() << "  Cannot rename " << MOP << " in " << MI);  in canRenameUpToDef()
1519         RequiredClasses.insert(TRI->getMinimalPhysRegClass(MOP.getReg()));  in canRenameUpToDef()
1523       for (auto &MOP : MI.operands()) {  in canRenameUpToDef()  local
1524         if (!MOP.isReg() || MOP.isDebug() || !MOP.getReg() ||  in canRenameUpToDef()
1525             !TRI->regsOverlap(MOP.getReg(), RegToRename))  in canRenameUpToDef()
1528         if (!canRenameMOP(MOP, TRI)) {  in canRenameUpToDef()
1529           LLVM_DEBUG(dbgs() << "  Cannot rename " << MOP << " in " << MI);  in canRenameUpToDef()
1532         RequiredClasses.insert(TRI->getMinimalPhysRegClass(MOP.getReg()));  in canRenameUpToDef()
1578         for (auto &MOP : MI.operands()) {  in canRenameUntilSecondLoad()  local
1579           if (!MOP.isReg() || MOP.isDebug() || !MOP.getReg() ||  in canRenameUntilSecondLoad()
1580               !TRI->regsOverlap(MOP.getReg(), RegToRename))  in canRenameUntilSecondLoad()
1582           if (!canRenameMOP(MOP, TRI)) {  in canRenameUntilSecondLoad()
1583             LLVM_DEBUG(dbgs() << "  Cannot rename " << MOP << " in " << MI);  in canRenameUntilSecondLoad()
1586           RequiredClasses.insert(TRI->getMinimalPhysRegClass(MOP.getReg()));  in canRenameUntilSecondLoad()