563 static bool isPreLdStPairCandidate(MachineInstr &FirstMI, MachineInstr &MI) {  in isPreLdStPairCandidate()  argument
565   unsigned OpcA = FirstMI.getOpcode();  in isPreLdStPairCandidate()
1359 static bool areCandidatesToMergeOrPair(MachineInstr &FirstMI, MachineInstr &MI,  in areCandidatesToMergeOrPair()  argument
1367   assert(!FirstMI.hasOrderedMemoryRef() &&  in areCandidatesToMergeOrPair()
1368          !TII->isLdStPairSuppressed(FirstMI) &&  in areCandidatesToMergeOrPair()
1375   unsigned OpcA = FirstMI.getOpcode();  in areCandidatesToMergeOrPair()
1380     return !AArch64InstrInfo::isPreLdSt(FirstMI);  in areCandidatesToMergeOrPair()
1383   if (AArch64InstrInfo::isPreLdSt(FirstMI) && AArch64InstrInfo::isPreLdSt(MI))  in areCandidatesToMergeOrPair()
1410   if (isPreLdStPairCandidate(FirstMI, MI))  in areCandidatesToMergeOrPair()
1453 canRenameUpToDef(MachineInstr &FirstMI, LiveRegUnits &UsedInBetween,  in canRenameUpToDef()  argument
1456   if (!FirstMI.mayStore())  in canRenameUpToDef()
1462   auto RegToRename = getLdStRegOp(FirstMI).getReg();  in canRenameUpToDef()
1464   if (!getLdStRegOp(FirstMI).isKill() &&  in canRenameUpToDef()
1465       !any_of(FirstMI.operands(),  in canRenameUpToDef()
1471     LLVM_DEBUG(dbgs() << "  Operand not killed at " << FirstMI);  in canRenameUpToDef()
1538   if (!forAllMIsUntilDef(FirstMI, RegToRename, TRI, LdStLimit, CheckMIs))  in canRenameUpToDef()
1646     std::optional<bool> MaybeCanRename, MachineInstr &FirstMI, MachineInstr &MI,  in findRenameRegForSameLdStRegPair()  argument
1654   auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg());  in findRenameRegForSameLdStRegPair()
1655   MachineFunction &MF = *FirstMI.getParent()->getParent();  in findRenameRegForSameLdStRegPair()
1659   const bool IsLoad = FirstMI.mayLoad();  in findRenameRegForSameLdStRegPair()
1663       MaybeCanRename = {canRenameUntilSecondLoad(FirstMI, MI, UsedInBetween,  in findRenameRegForSameLdStRegPair()
1667           canRenameUpToDef(FirstMI, UsedInBetween, RequiredClasses, TRI)};  in findRenameRegForSameLdStRegPair()
1686   MachineInstr &FirstMI = *I;  in findMatchingInsn()  local
1689   bool MayLoad = FirstMI.mayLoad();  in findMatchingInsn()
1690   bool IsUnscaled = TII->hasUnscaledLdStOffset(FirstMI);  in findMatchingInsn()
1691   Register Reg = getLdStRegOp(FirstMI).getReg();  in findMatchingInsn()
1692   Register BaseReg = AArch64InstrInfo::getLdStBaseOp(FirstMI).getReg();  in findMatchingInsn()
1693   int Offset = AArch64InstrInfo::getLdStOffsetOp(FirstMI).getImm();  in findMatchingInsn()
1694   int OffsetStride = IsUnscaled ? TII->getMemScale(FirstMI) : 1;  in findMatchingInsn()
1695   bool IsPromotableZeroStore = isPromotableZeroStoreInst(FirstMI);  in findMatchingInsn()
1715   LLVM_DEBUG(dbgs() << "Find match for: "; FirstMI.dump());  in findMatchingInsn()
1729     if (areCandidatesToMergeOrPair(FirstMI, MI, Flags, TII) &&  in findMatchingInsn()
1761       bool IsPreLdSt = isPreLdStPairCandidate(FirstMI, MI);  in findMatchingInsn()
1870                 findRenameRegForSameLdStRegPair(MaybeCanRename, FirstMI, MI,  in findMatchingInsn()
1895             MayLoad && !UsedRegUnits.available(getLdStRegOp(FirstMI).getReg()));  in findMatchingInsn()
1898                           << "Reg '" << getLdStRegOp(FirstMI)  in findMatchingInsn()
1902         if (RtNotModified && !mayAlias(FirstMI, MemInsns, AA)) {  in findMatchingInsn()
1903           if (ModifiedRegUnits.available(getLdStRegOp(FirstMI).getReg())) {  in findMatchingInsn()
1910               MaybeCanRename, FirstMI, MI, Reg, DefinedInBB, UsedInBetween,  in findMatchingInsn()