324   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();  in homogeneousPrologEpilog()  local
325   if (MFI.hasVarSizedObjects() || RegInfo->hasStackRealignment(MF))  in homogeneousPrologEpilog()
446   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();  in hasFP()  local
458       RegInfo->hasStackRealignment(MF))  in hasFP()
1045   const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();  in canUseAsPrologue()  local
1063   if (!RegInfo->hasStackRealignment(*MF) && TLI->hasInlineStackProbe(*MF))  in canUseAsPrologue()
1091   const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();  in shouldCombineCSRLocalStackBump()  local
1118   if (RegInfo->hasStackRealignment(MF))  in shouldCombineCSRLocalStackBump()
1181   const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();  in InsertSEH()  local
1190     unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());  in InsertSEH()
1191     unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg());  in InsertSEH()
1211                 .addImm(RegInfo->getSEHRegNum(Reg0))  in InsertSEH()
1212                 .addImm(RegInfo->getSEHRegNum(Reg1))  in InsertSEH()
1221     unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());  in InsertSEH()
1232     unsigned Reg =  RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());  in InsertSEH()
1241     unsigned Reg0 =  RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());  in InsertSEH()
1242     unsigned Reg1 =  RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());  in InsertSEH()
1260                 .addImm(RegInfo->getSEHRegNum(Reg0))  in InsertSEH()
1261                 .addImm(RegInfo->getSEHRegNum(Reg1))  in InsertSEH()
1268     int Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());  in InsertSEH()
1277     unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());  in InsertSEH()
1286     unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());  in InsertSEH()
1287     unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());  in InsertSEH()
1299     unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());  in InsertSEH()
1300     unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg());  in InsertSEH()
1620   const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();  in emitPrologue()  local
1907       NumBytes && !IsFunclet && RegInfo->hasStackRealignment(MF);  in emitPrologue()
2091   if (!IsFunclet && RegInfo->hasBasePointer(MF)) {  in emitPrologue()
2092     TII->copyPhysReg(MBB, MBBI, DL, RegInfo->getBaseRegister(), AArch64::SP,  in emitPrologue()
2128           *RegInfo, /*FrameReg=*/AArch64::SP, /*Reg=*/AArch64::SP, TotalSize,  in emitPrologue()
2332       const AArch64RegisterInfo &RegInfo = *Subtarget.getRegisterInfo();  in emitEpilogue()  local
2333       unsigned Reg = RegInfo.getDwarfRegNum(AArch64::SP, true);  in emitEpilogue()
2459     const AArch64RegisterInfo &RegInfo = *Subtarget.getRegisterInfo();  in emitEpilogue()  local
2460     unsigned Reg = RegInfo.getDwarfRegNum(AArch64::SP, true);  in emitEpilogue()
2531   const auto *RegInfo = static_cast<const AArch64RegisterInfo *>(  in getSEHFrameIndexOffset()  local
2534   return RegInfo->getLocalAddressRegister(MF) == AArch64::FP  in getSEHFrameIndexOffset()
2554   const auto *RegInfo = static_cast<const AArch64RegisterInfo *>(  in resolveFrameOffsetReference()  local
2583     } else if (isCSR && RegInfo->hasStackRealignment(MF)) {  in resolveFrameOffsetReference()
2589     } else if (hasFP(MF) && !RegInfo->hasStackRealignment(MF)) {  in resolveFrameOffsetReference()
2601         bool CanUseBP = RegInfo->hasBasePointer(MF);  in resolveFrameOffsetReference()
2614       } else if (MF.hasEHFunclets() && !RegInfo->hasBasePointer(MF)) {  in resolveFrameOffsetReference()
2632       ((isFixed || isCSR) || !RegInfo->hasStackRealignment(MF) || !UseFP) &&  in resolveFrameOffsetReference()
2646                       RegInfo->hasStackRealignment(MF))) {  in resolveFrameOffsetReference()
2647       FrameReg = RegInfo->getFrameRegister(MF);  in resolveFrameOffsetReference()
2651     FrameReg = RegInfo->hasBasePointer(MF) ? RegInfo->getBaseRegister()  in resolveFrameOffsetReference()
2663     FrameReg = RegInfo->getFrameRegister(MF);  in resolveFrameOffsetReference()
2668   if (RegInfo->hasBasePointer(MF))  in resolveFrameOffsetReference()
2669     FrameReg = RegInfo->getBaseRegister();  in resolveFrameOffsetReference()
3235   const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>(  in determineCalleeSaves()  local
3245   unsigned BasePointerReg = RegInfo->hasBasePointer(MF)  in determineCalleeSaves()
3246                                 ? RegInfo->getBaseRegister()  in determineCalleeSaves()
3287           !RegInfo->isReservedReg(MF, Reg)) {  in determineCalleeSaves()
3301           !RegInfo->isReservedReg(MF, PairedReg))  in determineCalleeSaves()
3344              << ' ' << printReg(Reg, RegInfo);  in determineCalleeSaves()
3368   if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF))  in determineCalleeSaves()
3379       LLVM_DEBUG(dbgs() << "Spilling " << printReg(UnspilledCSGPR, RegInfo)  in determineCalleeSaves()
3438     MachineFunction &MF, const TargetRegisterInfo *RegInfo,  in assignCalleeSavedSpillSlots()  argument
3468     const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);  in assignCalleeSavedSpillSlots()
3470     unsigned Size = RegInfo->getSpillSize(*RC);  in assignCalleeSavedSpillSlots()
3471     Align Alignment(RegInfo->getSpillAlign(*RC));  in assignCalleeSavedSpillSlots()
4400       const AArch64RegisterInfo &RegInfo =  in inlineStackProbeFixed()  local
4402       unsigned Reg = RegInfo.getDwarfRegNum(AArch64::SP, true);  in inlineStackProbeFixed()