Lines Matching refs:getOffsetReg
125 unsigned getOffsetReg() const { in getOffsetReg() function in __anon16c582f80111::AArch64FastISel::Address
724 if (Addr.getOffsetReg()) in computeAddress()
797 if (Addr.getOffsetReg()) in computeAddress()
858 if (Addr.getOffsetReg()) in computeAddress()
888 if (!Addr.getReg() || Addr.getOffsetReg()) in computeAddress()
925 if (!Addr.getOffsetReg()) { in computeAddress()
1052 if (!ImmediateOffsetNeedsLowering && Addr.getOffset() && Addr.getOffsetReg()) in simplifyAddress()
1056 if (Addr.isRegBase() && Addr.getOffsetReg() && !Addr.getReg()) in simplifyAddress()
1062 if ((ImmediateOffsetNeedsLowering || Addr.getOffsetReg()) && Addr.isFIBase()) in simplifyAddress()
1080 Addr.getOffsetReg(), Addr.getExtendType(), in simplifyAddress()
1084 Addr.getOffsetReg(), AArch64_AM::LSL, in simplifyAddress()
1088 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(), in simplifyAddress()
1091 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(), in simplifyAddress()
1094 ResultReg = emitLSL_ri(MVT::i64, MVT::i64, Addr.getOffsetReg(), in simplifyAddress()
1147 constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1)); in addLoadStoreOperands()
1148 if (Addr.getOffsetReg()) { in addLoadStoreOperands()
1153 MIB.addReg(Addr.getOffsetReg()); in addLoadStoreOperands()
1821 Addr.getOffsetReg(); in emitLoad()
2111 Addr.getOffsetReg(); in emitStore()