Lines Matching refs:RHSReg
207 unsigned RHSReg, bool SetFlags = false,
213 unsigned RHSReg, AArch64_AM::ShiftExtendType ShiftType,
217 unsigned RHSReg, AArch64_AM::ShiftExtendType ExtType,
242 unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
244 unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
252 unsigned RHSReg, uint64_t ShiftImm);
1234 Register RHSReg = getRegForValue(RHS); in emitAddSub() local
1235 if (!RHSReg) in emitAddSub()
1237 return emitAddSub_rx(UseAdd, RetVT, LHSReg, RHSReg, ExtendType, 0, in emitAddSub()
1253 Register RHSReg = getRegForValue(MulLHS); in emitAddSub() local
1254 if (!RHSReg) in emitAddSub()
1256 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, AArch64_AM::LSL, in emitAddSub()
1276 Register RHSReg = getRegForValue(SI->getOperand(0)); in emitAddSub() local
1277 if (!RHSReg) in emitAddSub()
1279 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, ShiftType, in emitAddSub()
1288 Register RHSReg = getRegForValue(RHS); in emitAddSub() local
1289 if (!RHSReg) in emitAddSub()
1293 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1295 return emitAddSub_rr(UseAdd, RetVT, LHSReg, RHSReg, SetFlags, WantResult); in emitAddSub()
1299 unsigned RHSReg, bool SetFlags, in emitAddSub_rr() argument
1301 assert(LHSReg && RHSReg && "Invalid register number."); in emitAddSub_rr()
1304 RHSReg == AArch64::SP || RHSReg == AArch64::WSP) in emitAddSub_rr()
1328 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rr()
1331 .addReg(RHSReg); in emitAddSub_rr()
1381 unsigned RHSReg, in emitAddSub_rs() argument
1385 assert(LHSReg && RHSReg && "Invalid register number."); in emitAddSub_rs()
1387 RHSReg != AArch64::SP && RHSReg != AArch64::WSP); in emitAddSub_rs()
1414 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rs()
1417 .addReg(RHSReg) in emitAddSub_rs()
1423 unsigned RHSReg, in emitAddSub_rx() argument
1427 assert(LHSReg && RHSReg && "Invalid register number."); in emitAddSub_rx()
1429 RHSReg != AArch64::XZR && RHSReg != AArch64::WZR); in emitAddSub_rx()
1458 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rx()
1461 .addReg(RHSReg) in emitAddSub_rx()
1521 Register RHSReg = getRegForValue(RHS); in emitFCmp() local
1522 if (!RHSReg) in emitFCmp()
1528 .addReg(RHSReg); in emitFCmp()
1568 unsigned RHSReg, bool WantResult) { in emitSubs_rr() argument
1569 return emitAddSub_rr(/*UseAdd=*/false, RetVT, LHSReg, RHSReg, in emitSubs_rr()
1574 unsigned RHSReg, in emitSubs_rs() argument
1577 return emitAddSub_rs(/*UseAdd=*/false, RetVT, LHSReg, RHSReg, ShiftType, in emitSubs_rs()
1623 Register RHSReg = getRegForValue(MulLHS); in emitLogicalOp() local
1624 if (!RHSReg) in emitLogicalOp()
1626 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal); in emitLogicalOp()
1637 Register RHSReg = getRegForValue(SI->getOperand(0)); in emitLogicalOp() local
1638 if (!RHSReg) in emitLogicalOp()
1640 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal); in emitLogicalOp()
1646 Register RHSReg = getRegForValue(RHS); in emitLogicalOp() local
1647 if (!RHSReg) in emitLogicalOp()
1651 ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, RHSReg); in emitLogicalOp()
1705 unsigned LHSReg, unsigned RHSReg, in emitLogicalOp_rs() argument
1737 fastEmitInst_rri(Opc, RC, LHSReg, RHSReg, in emitLogicalOp_rs()
3704 Register RHSReg = getRegForValue(RHS); in fastLowerIntrinsicCall() local
3705 if (!RHSReg) in fastLowerIntrinsicCall()
3709 MulReg = emitSMULL_rr(MVT::i64, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3721 MulReg = emitMul_rr(VT, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3722 unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3734 Register RHSReg = getRegForValue(RHS); in fastLowerIntrinsicCall() local
3735 if (!RHSReg) in fastLowerIntrinsicCall()
3739 MulReg = emitUMULL_rr(MVT::i64, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3750 MulReg = emitMul_rr(VT, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3751 unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3818 Register RHSReg = getRegForValue(II->getArgOperand(1)); in fastLowerIntrinsicCall() local
3819 if (!LHSReg || !RHSReg) in fastLowerIntrinsicCall()
3823 fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, LHSReg, RHSReg); in fastLowerIntrinsicCall()