206   unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
209   unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
212   unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
216   unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
225   bool emitICmp_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm);
242   unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
244   unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
249   unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
251   unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
253   unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm);
1208   Register LHSReg = getRegForValue(LHS);  in emitAddSub()  local
1209   if (!LHSReg)  in emitAddSub()
1213     LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt);  in emitAddSub()
1219       ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, -Imm, SetFlags,  in emitAddSub()
1222       ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, Imm, SetFlags,  in emitAddSub()
1226       ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, 0, SetFlags, WantResult);  in emitAddSub()
1237     return emitAddSub_rx(UseAdd, RetVT, LHSReg, RHSReg, ExtendType, 0,  in emitAddSub()
1256       ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, AArch64_AM::LSL,  in emitAddSub()
1279           ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, ShiftType,  in emitAddSub()
1295   return emitAddSub_rr(UseAdd, RetVT, LHSReg, RHSReg, SetFlags, WantResult);  in emitAddSub()
1298 unsigned AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,  in emitAddSub_rr()  argument
1301   assert(LHSReg && RHSReg && "Invalid register number.");  in emitAddSub_rr()
1303   if (LHSReg == AArch64::SP || LHSReg == AArch64::WSP ||  in emitAddSub_rr()
1327   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());  in emitAddSub_rr()
1330       .addReg(LHSReg)  in emitAddSub_rr()
1335 unsigned AArch64FastISel::emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,  in emitAddSub_ri()  argument
1338   assert(LHSReg && "Invalid register number.");  in emitAddSub_ri()
1372   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());  in emitAddSub_ri()
1374       .addReg(LHSReg)  in emitAddSub_ri()
1380 unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,  in emitAddSub_rs()  argument
1385   assert(LHSReg && RHSReg && "Invalid register number.");  in emitAddSub_rs()
1386   assert(LHSReg != AArch64::SP && LHSReg != AArch64::WSP &&  in emitAddSub_rs()
1413   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());  in emitAddSub_rs()
1416       .addReg(LHSReg)  in emitAddSub_rs()
1422 unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,  in emitAddSub_rx()  argument
1427   assert(LHSReg && RHSReg && "Invalid register number.");  in emitAddSub_rx()
1428   assert(LHSReg != AArch64::XZR && LHSReg != AArch64::WZR &&  in emitAddSub_rx()
1457   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());  in emitAddSub_rx()
1460       .addReg(LHSReg)  in emitAddSub_rx()
1494 bool AArch64FastISel::emitICmp_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm) {  in emitICmp_ri()  argument
1495   return emitAddSub_ri(/*UseAdd=*/false, RetVT, LHSReg, Imm,  in emitICmp_ri()
1510   Register LHSReg = getRegForValue(LHS);  in emitFCmp()  local
1511   if (!LHSReg)  in emitFCmp()
1517         .addReg(LHSReg);  in emitFCmp()
1527       .addReg(LHSReg)  in emitFCmp()
1567 unsigned AArch64FastISel::emitSubs_rr(MVT RetVT, unsigned LHSReg,  in emitSubs_rr()  argument
1569   return emitAddSub_rr(/*UseAdd=*/false, RetVT, LHSReg, RHSReg,  in emitSubs_rr()
1573 unsigned AArch64FastISel::emitSubs_rs(MVT RetVT, unsigned LHSReg,  in emitSubs_rs()  argument
1577   return emitAddSub_rs(/*UseAdd=*/false, RetVT, LHSReg, RHSReg, ShiftType,  in emitSubs_rs()
1598   Register LHSReg = getRegForValue(LHS);  in emitLogicalOp()  local
1599   if (!LHSReg)  in emitLogicalOp()
1605     ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, Imm);  in emitLogicalOp()
1626       ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);  in emitLogicalOp()
1640         ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);  in emitLogicalOp()
1651   ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, RHSReg);  in emitLogicalOp()
1660                                            unsigned LHSReg, uint64_t Imm) {  in emitLogicalOp_ri()  argument
1695       fastEmitInst_ri(Opc, RC, LHSReg,  in emitLogicalOp_ri()
1705                                            unsigned LHSReg, unsigned RHSReg,  in emitLogicalOp_rs()  argument
1737       fastEmitInst_rri(Opc, RC, LHSReg, RHSReg,  in emitLogicalOp_rs()
1746 unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg,  in emitAnd_ri()  argument
1748   return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, Imm);  in emitAnd_ri()
3700       Register LHSReg = getRegForValue(LHS);  in fastLowerIntrinsicCall()  local
3701       if (!LHSReg)  in fastLowerIntrinsicCall()
3709         MulReg = emitSMULL_rr(MVT::i64, LHSReg, RHSReg);  in fastLowerIntrinsicCall()
3721         MulReg = emitMul_rr(VT, LHSReg, RHSReg);  in fastLowerIntrinsicCall()
3722         unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, RHSReg);  in fastLowerIntrinsicCall()
3730       Register LHSReg = getRegForValue(LHS);  in fastLowerIntrinsicCall()  local
3731       if (!LHSReg)  in fastLowerIntrinsicCall()
3739         MulReg = emitUMULL_rr(MVT::i64, LHSReg, RHSReg);  in fastLowerIntrinsicCall()
3750         MulReg = emitMul_rr(VT, LHSReg, RHSReg);  in fastLowerIntrinsicCall()
3751         unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, RHSReg);  in fastLowerIntrinsicCall()
3817     Register LHSReg = getRegForValue(II->getArgOperand(0));  in fastLowerIntrinsicCall()  local
3819     if (!LHSReg || !RHSReg)  in fastLowerIntrinsicCall()
3823         fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, LHSReg, RHSReg);  in fastLowerIntrinsicCall()