247   unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
249   unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
251   unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
1581 unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,  in emitLogicalOp()  argument
1605     ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, Imm);  in emitLogicalOp()
1626       ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);  in emitLogicalOp()
1640         ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);  in emitLogicalOp()
1651   ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, RHSReg);  in emitLogicalOp()
1659 unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT,  in emitLogicalOp_ri()  argument
1678     unsigned Idx = ISDOpc - ISD::AND;  in emitLogicalOp_ri()
1685     Opc = OpcTable[ISDOpc - ISD::AND][1];  in emitLogicalOp_ri()
1697   if (RetVT >= MVT::i8 && RetVT <= MVT::i16 && ISDOpc != ISD::AND) {  in emitLogicalOp_ri()
1704 unsigned AArch64FastISel::emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT,  in emitLogicalOp_rs()  argument
1728     Opc = OpcTable[ISDOpc - ISD::AND][0];  in emitLogicalOp_rs()
1732     Opc = OpcTable[ISDOpc - ISD::AND][1];  in emitLogicalOp_rs()