138   bool regsAreCompatible(Register RegA, Register RegB) const;
147   bool isProfitableToCommute(Register RegA, Register RegB, Register RegC,
153   bool isProfitableToConv3Addr(Register RegA, Register RegB);
156                           MachineBasicBlock::iterator &nmi, Register RegA,
471 bool TwoAddressInstructionPass::regsAreCompatible(Register RegA,  in regsAreCompatible()  argument
473   if (RegA == RegB)  in regsAreCompatible()
475   if (!RegA || !RegB)  in regsAreCompatible()
477   return TRI->regsOverlap(RegA, RegB);  in regsAreCompatible()
560 bool TwoAddressInstructionPass::isProfitableToCommute(Register RegA,  in isProfitableToCommute()  argument
599   MCRegister ToRegA = getMappedReg(RegA, DstRegMap);  in isProfitableToCommute()
647   if (isRevCopyChain(RegC, RegA, MaxDataFlowEdge))  in isProfitableToCommute()
650   if (isRevCopyChain(RegB, RegA, MaxDataFlowEdge))  in isProfitableToCommute()
687     Register RegA = MI->getOperand(DstIdx).getReg();  in commuteInstruction()  local
688     SrcRegMap[RegA] = FromRegC;  in commuteInstruction()
696 bool TwoAddressInstructionPass::isProfitableToConv3Addr(Register RegA,  in isProfitableToConv3Addr()  argument
707   MCRegister ToRegA = getMappedReg(RegA, DstRegMap);  in isProfitableToConv3Addr()
715     Register RegA, Register RegB, unsigned &Dist) {  in convertInstTo3Addr()  argument
748   SrcRegMap.erase(RegA);  in convertInstTo3Addr()
1496     Register RegA = DstMO.getReg();  in processTiedPairs()  local
1503     if (RegA == RegB) {  in processTiedPairs()
1510     LastCopiedReg = RegA;  in processTiedPairs()
1521              MI->getOperand(i).getReg() != RegA);  in processTiedPairs()
1526                                       TII->get(TargetOpcode::COPY), RegA);  in processTiedPairs()
1532       if (RegA.isVirtual()) {  in processTiedPairs()
1533         assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),  in processTiedPairs()
1539         assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))  in processTiedPairs()
1555       if (RegA.isVirtual()) {  in processTiedPairs()
1556         LiveInterval &LI = LIS->getInterval(RegA);  in processTiedPairs()
1564         for (MCRegUnit Unit : TRI->regunits(RegA)) {  in processTiedPairs()
1585     if (RegA.isVirtual() && RegB.isVirtual())  in processTiedPairs()
1586       MRI->constrainRegClass(RegA, RC);  in processTiedPairs()
1587     MO.setReg(RegA);  in processTiedPairs()
1681     Register RegA = DstMO.getReg();  in processStatepoint()  local
1685     if (RegA == RegB)  in processStatepoint()
1695       const auto &DefLI = LIS->getInterval(RegA);  in processStatepoint()
1712     if (!MRI->constrainRegClass(RegB, MRI->getRegClass(RegA))) {  in processStatepoint()
1714                         << " to register class of " << printReg(RegA, TRI, 0)  in processStatepoint()
1719     MRI->replaceRegWith(RegA, RegB);  in processStatepoint()
1724       LiveInterval &Other = LIS->getInterval(RegA);  in processStatepoint()
1735       LIS->removeInterval(RegA);  in processStatepoint()
1742       LiveVariables::VarInfo &DstInfo = LV->getVarInfo(RegA);  in processStatepoint()