Lines Matching refs:isBeforeLegalizeOps
618 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedBits()
634 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedBits()
2942 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedVectorElts()
3981 if (DCI.isBeforeLegalizeOps() || in foldSetCCWithAnd()
4425 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4434 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4684 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4737 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4866 if ((DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4886 if ((DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4902 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { in SimplifySetCC()
4920 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { in SimplifySetCC()
5005 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { in SimplifySetCC()
5129 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
5190 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
6579 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::MUL, VT)) in prepareUREMEqFold()
6716 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::SUB, VT)) in prepareUREMEqFold()
6731 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ROTR, VT)) in prepareUREMEqFold()
6829 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::MUL, VT)) in prepareSREMEqFold()
6984 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ADD, VT)) in prepareSREMEqFold()
6996 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ROTR, VT)) in prepareSREMEqFold()