Lines Matching refs:LegalOps
2311 if (DemandedBits.isOne() && !TLO.LegalOps && !VT.isVector()) in SimplifyDemandedBits()
3443 if (Updated && !IdentityLHS && !IdentityRHS && !TLO.LegalOps) { in SimplifyDemandedVectorElts()
7092 bool LegalOps, bool OptForSize, in getNegatedExpression() argument
7141 if (LegalOps && !IsOpLegal) in getNegatedExpression()
7171 if (LegalOps && !IsOpLegal) in getNegatedExpression()
7192 if (LegalOps && !isOperationLegalOrCustom(ISD::FSUB, VT)) in getNegatedExpression()
7199 getNegatedExpression(X, DAG, LegalOps, OptForSize, CostX, Depth); in getNegatedExpression()
7207 getNegatedExpression(Y, DAG, LegalOps, OptForSize, CostY, Depth); in getNegatedExpression()
7255 getNegatedExpression(X, DAG, LegalOps, OptForSize, CostX, Depth); in getNegatedExpression()
7263 getNegatedExpression(Y, DAG, LegalOps, OptForSize, CostY, Depth); in getNegatedExpression()
7300 getNegatedExpression(Z, DAG, LegalOps, OptForSize, CostZ, Depth); in getNegatedExpression()
7311 getNegatedExpression(X, DAG, LegalOps, OptForSize, CostX, Depth); in getNegatedExpression()
7319 getNegatedExpression(Y, DAG, LegalOps, OptForSize, CostY, Depth); in getNegatedExpression()
7346 if (SDValue NegV = getNegatedExpression(Op.getOperand(0), DAG, LegalOps, in getNegatedExpression()
7351 if (SDValue NegV = getNegatedExpression(Op.getOperand(0), DAG, LegalOps, in getNegatedExpression()
7362 getNegatedExpression(LHS, DAG, LegalOps, OptForSize, CostLHS, Depth); in getNegatedExpression()
7374 getNegatedExpression(RHS, DAG, LegalOps, OptForSize, CostRHS, Depth); in getNegatedExpression()