Lines Matching refs:IsLE
681 bool IsLE = DAG.getDataLayout().isLittleEndian(); in SimplifyMultipleUseDemandedBits() local
709 unsigned EltOffset = IsLE ? i : (Scale - 1 - i); in SimplifyMultipleUseDemandedBits()
726 if (IsLE && (NumSrcEltBits % NumDstEltBits) == 0) { in SimplifyMultipleUseDemandedBits()
844 if (IsLE && DemandedElts == 1 && in SimplifyMultipleUseDemandedBits()
1091 bool IsLE = TLO.DAG.getDataLayout().isLittleEndian(); in SimplifyDemandedBits() local
2405 if (IsLE && IsVecInReg && DemandedElts == 1 && in SimplifyDemandedBits()
2458 if (IsLE && IsVecInReg && DemandedElts == 1 && in SimplifyDemandedBits()
2513 if (IsLE && IsVecInReg && DemandedElts == 1 && in SimplifyDemandedBits()
2685 unsigned EltOffset = IsLE ? i : (Scale - 1 - i); in SimplifyDemandedBits()
2705 } else if (IsLE && (NumSrcEltBits % BitWidth) == 0) { in SimplifyDemandedBits()
3048 bool IsLE = TLO.DAG.getDataLayout().isLittleEndian(); in SimplifyDemandedVectorElts() local
3125 if (IsLE) { in SimplifyDemandedVectorElts()
3482 if (IsLE && Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG && in SimplifyDemandedVectorElts()
3497 if (IsLE && DemandedSrcElts == 1 && Src.getOpcode() == ISD::AND && in SimplifyDemandedVectorElts()