Lines Matching refs:DemandedRHS
1329 APInt DemandedLHS, DemandedRHS; in SimplifyDemandedBits() local
1331 DemandedRHS)) in SimplifyDemandedBits()
1334 if (!!DemandedLHS || !!DemandedRHS) { in SimplifyDemandedBits()
1346 if (!!DemandedRHS) { in SimplifyDemandedBits()
1347 if (SimplifyDemandedBits(Op1, DemandedBits, DemandedRHS, Known2, TLO, in SimplifyDemandedBits()
1357 Op1, DemandedBits, DemandedRHS, TLO.DAG, Depth + 1); in SimplifyDemandedBits()
3372 APInt DemandedRHS(DemandedElts); in SimplifyDemandedVectorElts() local
3378 if (SimplifyDemandedVectorElts(RHS, DemandedRHS, UndefRHS, ZeroRHS, TLO, in SimplifyDemandedVectorElts()
3402 APInt DemandedRHS(NumElts, 0); in SimplifyDemandedVectorElts() local
3411 DemandedRHS.setBit(M - NumElts); in SimplifyDemandedVectorElts()
3420 if (SimplifyDemandedVectorElts(RHS, DemandedRHS, UndefRHS, ZeroRHS, TLO, in SimplifyDemandedVectorElts()