Lines Matching refs:DemandedElts
514 const APInt &DemandedElts, in ShrinkDemandedConstant() argument
521 if (DemandedBits.isZero() || DemandedElts.isZero()) in ShrinkDemandedConstant()
525 if (targetShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO)) in ShrinkDemandedConstant()
562 APInt DemandedElts = VT.isVector() in ShrinkDemandedConstant() local
565 return ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO); in ShrinkDemandedConstant()
630 const APInt &DemandedElts, in SimplifyDemandedBits() argument
638 SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO); in SimplifyDemandedBits()
656 APInt DemandedElts = VT.isFixedLengthVector() in SimplifyDemandedBits() local
659 return SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO, Depth, in SimplifyDemandedBits()
665 SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, in SimplifyMultipleUseDemandedBits() argument
678 if (DemandedBits == 0 || DemandedElts == 0) in SimplifyMultipleUseDemandedBits()
682 unsigned NumElts = DemandedElts.getBitWidth(); in SimplifyMultipleUseDemandedBits()
700 Src, DemandedBits, DemandedElts, DAG, Depth + 1)) in SimplifyMultipleUseDemandedBits()
715 if (DemandedElts[j]) in SimplifyMultipleUseDemandedBits()
732 if (DemandedElts[i]) { in SimplifyMultipleUseDemandedBits()
746 LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1); in SimplifyMultipleUseDemandedBits()
747 RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1); in SimplifyMultipleUseDemandedBits()
759 LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1); in SimplifyMultipleUseDemandedBits()
760 RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1); in SimplifyMultipleUseDemandedBits()
772 LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1); in SimplifyMultipleUseDemandedBits()
773 RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1); in SimplifyMultipleUseDemandedBits()
787 DAG.getValidMaximumShiftAmountConstant(Op, DemandedElts)) { in SimplifyMultipleUseDemandedBits()
791 DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1); in SimplifyMultipleUseDemandedBits()
828 unsigned NumSignBits = DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1); in SimplifyMultipleUseDemandedBits()
844 if (IsLE && DemandedElts == 1 && in SimplifyMultipleUseDemandedBits()
860 !DemandedElts[CIdx->getZExtValue()]) in SimplifyMultipleUseDemandedBits()
872 APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx); in SimplifyMultipleUseDemandedBits()
887 if (M < 0 || !DemandedElts[i]) in SimplifyMultipleUseDemandedBits()
910 Op, DemandedBits, DemandedElts, DAG, Depth)) in SimplifyMultipleUseDemandedBits()
924 APInt DemandedElts = VT.isFixedLengthVector() in SimplifyMultipleUseDemandedBits() local
927 return SimplifyMultipleUseDemandedBits(Op, DemandedBits, DemandedElts, DAG, in SimplifyMultipleUseDemandedBits()
932 SDValue Op, const APInt &DemandedElts, SelectionDAG &DAG, in SimplifyMultipleUseDemandedVectorElts() argument
935 return SimplifyMultipleUseDemandedBits(Op, DemandedBits, DemandedElts, DAG, in SimplifyMultipleUseDemandedVectorElts()
944 const APInt &DemandedElts, in combineShiftToAVG() argument
949 ConstantSDNode *N1C = isConstOrConstSplat(Op.getOperand(1), DemandedElts); in combineShiftToAVG()
968 if ((ConstOp = isConstOrConstSplat(Op2, DemandedElts)) && in combineShiftToAVG()
975 if ((ConstOp = isConstOrConstSplat(Op3, DemandedElts)) && in combineShiftToAVG()
999 unsigned NumSignedA = DAG.ComputeNumSignBits(ExtOpA, DemandedElts, Depth); in combineShiftToAVG()
1000 unsigned NumSignedB = DAG.ComputeNumSignBits(ExtOpB, DemandedElts, Depth); in combineShiftToAVG()
1003 DAG.computeKnownBits(ExtOpA, DemandedElts, Depth).countMinLeadingZeros(); in combineShiftToAVG()
1005 DAG.computeKnownBits(ExtOpB, DemandedElts, Depth).countMinLeadingZeros(); in combineShiftToAVG()
1097 APInt DemandedElts = OriginalDemandedElts; in SimplifyDemandedBits() local
1131 DemandedElts = APInt::getAllOnes(NumElts); in SimplifyDemandedBits()
1146 if (!DemandedElts[0]) in SimplifyDemandedBits()
1158 if (DemandedElts == 1) in SimplifyDemandedBits()
1165 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); in SimplifyDemandedBits()
1182 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); in SimplifyDemandedBits()
1204 APInt DemandedVecElts(DemandedElts); in SimplifyDemandedBits()
1210 if (!DemandedElts[Idx]) in SimplifyDemandedBits()
1241 APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx); in SimplifyDemandedBits()
1242 APInt DemandedSrcElts = DemandedElts; in SimplifyDemandedBits()
1286 APInt DemandedSrcElts = DemandedElts.zext(NumSrcElts).shl(Idx); in SimplifyDemandedBits()
1314 DemandedElts.extractBits(NumSubElts, i * NumSubElts); in SimplifyDemandedBits()
1330 if (!getShuffleDemandedElts(NumElts, ShuffleMask, DemandedElts, DemandedLHS, in SimplifyDemandedBits()
1377 KnownBits LHSKnown = TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth); in SimplifyDemandedBits()
1386 DemandedElts, TLO)) in SimplifyDemandedBits()
1413 TLO.DAG.computeKnownBits(Op1, DemandedSub & DemandedElts, Depth + 1); in SimplifyDemandedBits()
1424 if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO, in SimplifyDemandedBits()
1428 if (SimplifyDemandedBits(Op0, ~Known.Zero & DemandedBits, DemandedElts, in SimplifyDemandedBits()
1443 if (ShrinkDemandedConstant(Op, ~Known2.Zero & DemandedBits, DemandedElts, in SimplifyDemandedBits()
1451 if (!DemandedBits.isAllOnes() || !DemandedElts.isAllOnes()) { in SimplifyDemandedBits()
1453 Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); in SimplifyDemandedBits()
1455 Op1, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); in SimplifyDemandedBits()
1471 if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO, in SimplifyDemandedBits()
1480 if (SimplifyDemandedBits(Op0, ~Known.One & DemandedBits, DemandedElts, in SimplifyDemandedBits()
1497 if (ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO)) in SimplifyDemandedBits()
1504 if (!DemandedBits.isAllOnes() || !DemandedElts.isAllOnes()) { in SimplifyDemandedBits()
1506 Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); in SimplifyDemandedBits()
1508 Op1, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); in SimplifyDemandedBits()
1551 if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO, in SimplifyDemandedBits()
1555 if (SimplifyDemandedBits(Op0, DemandedBits, DemandedElts, Known2, TLO, in SimplifyDemandedBits()
1576 ConstantSDNode *C = isConstOrConstSplat(Op1, DemandedElts); in SimplifyDemandedBits()
1601 isConstOrConstSplat(Op0.getOperand(1), DemandedElts)) { in SimplifyDemandedBits()
1627 if (ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO)) in SimplifyDemandedBits()
1631 if (!DemandedBits.isAllOnes() || !DemandedElts.isAllOnes()) { in SimplifyDemandedBits()
1633 Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); in SimplifyDemandedBits()
1635 Op1, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); in SimplifyDemandedBits()
1648 if (SimplifyDemandedBits(Op.getOperand(2), DemandedBits, DemandedElts, in SimplifyDemandedBits()
1651 if (SimplifyDemandedBits(Op.getOperand(1), DemandedBits, DemandedElts, in SimplifyDemandedBits()
1658 if (ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO)) in SimplifyDemandedBits()
1665 if (SimplifyDemandedBits(Op.getOperand(2), DemandedBits, DemandedElts, in SimplifyDemandedBits()
1668 if (SimplifyDemandedBits(Op.getOperand(1), DemandedBits, DemandedElts, in SimplifyDemandedBits()
1678 if (SimplifyDemandedBits(Op.getOperand(3), DemandedBits, DemandedElts, in SimplifyDemandedBits()
1681 if (SimplifyDemandedBits(Op.getOperand(2), DemandedBits, DemandedElts, in SimplifyDemandedBits()
1688 if (ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO)) in SimplifyDemandedBits()
1728 TLO.DAG.getValidShiftAmountConstant(Op, DemandedElts)) { in SimplifyDemandedBits()
1740 TLO.DAG.getValidShiftAmountConstant(Op0, DemandedElts)) { in SimplifyDemandedBits()
1780 TLO.DAG.getValidShiftAmountConstant(InnerOp, DemandedElts)) { in SimplifyDemandedBits()
1798 if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO, in SimplifyDemandedBits()
1817 if (!InDemandedMask.isAllOnes() || !DemandedElts.isAllOnes()) { in SimplifyDemandedBits()
1819 Op0, InDemandedMask, DemandedElts, TLO.DAG, Depth + 1); in SimplifyDemandedBits()
1868 if (SimplifyDemandedBits(Op0, DemandedFromOp, DemandedElts, Known, TLO, in SimplifyDemandedBits()
1887 TLO.DAG.getValidMaximumShiftAmountConstant(Op, DemandedElts)) { in SimplifyDemandedBits()
1890 TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1); in SimplifyDemandedBits()
1904 DemandedElts, Depth + 1)) in SimplifyDemandedBits()
1908 TLO.DAG.getValidShiftAmountConstant(Op, DemandedElts)) { in SimplifyDemandedBits()
1920 TLO.DAG.getValidShiftAmountConstant(Op0, DemandedElts)) { in SimplifyDemandedBits()
1964 if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO, in SimplifyDemandedBits()
1974 if (!InDemandedMask.isAllOnes() || !DemandedElts.isAllOnes()) { in SimplifyDemandedBits()
1976 Op0, InDemandedMask, DemandedElts, TLO.DAG, Depth + 1); in SimplifyDemandedBits()
1985 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); in SimplifyDemandedBits()
1997 if (TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1) >= in SimplifyDemandedBits()
2010 DemandedElts, Depth + 1)) in SimplifyDemandedBits()
2014 TLO.DAG.getValidShiftAmountConstant(Op, DemandedElts)) { in SimplifyDemandedBits()
2023 TLO.DAG.getValidShiftAmountConstant(Op0, DemandedElts)) { in SimplifyDemandedBits()
2041 TLO.DAG.ComputeNumSignBits(Op0.getOperand(0), DemandedElts); in SimplifyDemandedBits()
2060 if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO, in SimplifyDemandedBits()
2089 if (!InDemandedMask.isAllOnes() || !DemandedElts.isAllOnes()) { in SimplifyDemandedBits()
2091 Op0, InDemandedMask, DemandedElts, TLO.DAG, Depth + 1); in SimplifyDemandedBits()
2107 if (ConstantSDNode *SA = isConstOrConstSplat(Op2, DemandedElts)) { in SimplifyDemandedBits()
2113 if (SimplifyDemandedBits(IsFSHL ? Op0 : Op1, DemandedBits, DemandedElts, in SimplifyDemandedBits()
2123 if (SimplifyDemandedBits(Op0, Demanded0, DemandedElts, Known2, TLO, in SimplifyDemandedBits()
2126 if (SimplifyDemandedBits(Op1, Demanded1, DemandedElts, Known, TLO, in SimplifyDemandedBits()
2138 !DemandedElts.isAllOnes()) { in SimplifyDemandedBits()
2140 Op0, Demanded0, DemandedElts, TLO.DAG, Depth + 1); in SimplifyDemandedBits()
2142 Op1, Demanded1, DemandedElts, TLO.DAG, Depth + 1); in SimplifyDemandedBits()
2156 if (SimplifyDemandedBits(Op2, DemandedAmtBits, DemandedElts, in SimplifyDemandedBits()
2169 if (BitWidth == TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1)) in SimplifyDemandedBits()
2172 if (ConstantSDNode *SA = isConstOrConstSplat(Op1, DemandedElts)) { in SimplifyDemandedBits()
2179 if (SimplifyDemandedBits(Op0, Demanded0, DemandedElts, Known2, TLO, in SimplifyDemandedBits()
2203 if (SimplifyDemandedBits(Op1, DemandedAmtBits, DemandedElts, Known2, TLO, in SimplifyDemandedBits()
2221 std::min(TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1), in SimplifyDemandedBits()
2222 TLO.DAG.ComputeNumSignBits(Op1, DemandedElts, Depth + 1)); in SimplifyDemandedBits()
2228 KnownBits Known0 = TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth + 1); in SimplifyDemandedBits()
2229 KnownBits Known1 = TLO.DAG.computeKnownBits(Op1, DemandedElts, Depth + 1); in SimplifyDemandedBits()
2265 if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedElts, Known2, TLO, in SimplifyDemandedBits()
2300 if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedElts, Known2, TLO, in SimplifyDemandedBits()
2315 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); in SimplifyDemandedBits()
2326 TLO.DAG.ComputeMaxSignificantBits(Op0, DemandedElts, Depth + 1); in SimplifyDemandedBits()
2350 if (SimplifyDemandedBits(Op0, InputDemandedBits, DemandedElts, Known, TLO, in SimplifyDemandedBits()
2405 if (IsLE && IsVecInReg && DemandedElts == 1 && in SimplifyDemandedBits()
2417 APInt InDemandedElts = DemandedElts.zext(InElts); in SimplifyDemandedBits()
2447 APInt InDemandedElts = DemandedElts.zext(InElts); in SimplifyDemandedBits()
2458 if (IsLE && IsVecInReg && DemandedElts == 1 && in SimplifyDemandedBits()
2513 if (IsLE && IsVecInReg && DemandedElts == 1 && in SimplifyDemandedBits()
2518 APInt InDemandedElts = DemandedElts.zext(InElts); in SimplifyDemandedBits()
2539 if (SimplifyDemandedBits(Src, TruncMask, DemandedElts, Known, TLO, in SimplifyDemandedBits()
2546 Src, TruncMask, DemandedElts, TLO.DAG, Depth + 1)) in SimplifyDemandedBits()
2564 TLO.DAG.getValidShiftAmountConstant(Src, DemandedElts); in SimplifyDemandedBits()
2691 if (DemandedElts[j]) in SimplifyDemandedBits()
2712 if (DemandedElts[i]) { in SimplifyDemandedBits()
2743 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); in SimplifyDemandedBits()
2754 ConstantSDNode *C = isConstOrConstSplat(Op.getOperand(1), DemandedElts); in SimplifyDemandedBits()
2780 if (SimplifyDemandedBits(Op0, LoMask, DemandedElts, KnownOp0, TLO, in SimplifyDemandedBits()
2782 SimplifyDemandedBits(Op1, LoMask, DemandedElts, KnownOp1, TLO, in SimplifyDemandedBits()
2802 if (!LoMask.isAllOnes() || !DemandedElts.isAllOnes()) { in SimplifyDemandedBits()
2804 Op0, LoMask, DemandedElts, TLO.DAG, Depth + 1); in SimplifyDemandedBits()
2806 Op1, LoMask, DemandedElts, TLO.DAG, Depth + 1); in SimplifyDemandedBits()
2896 if (SimplifyDemandedBitsForTargetNode(Op, DemandedBits, DemandedElts, in SimplifyDemandedBits()
2903 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); in SimplifyDemandedBits()
2938 const APInt &DemandedElts, in SimplifyDemandedVectorElts() argument
2946 SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero, TLO); in SimplifyDemandedVectorElts()
3009 APInt DemandedElts = OriginalDemandedElts; in SimplifyDemandedVectorElts() local
3010 unsigned NumElts = DemandedElts.getBitWidth(); in SimplifyDemandedVectorElts()
3034 DemandedElts.setAllBits(); in SimplifyDemandedVectorElts()
3037 if (DemandedElts == 0) { in SimplifyDemandedVectorElts()
3053 SDValue NewOp0 = SimplifyMultipleUseDemandedVectorElts(Op0, DemandedElts, in SimplifyDemandedVectorElts()
3055 SDValue NewOp1 = SimplifyMultipleUseDemandedVectorElts(Op1, DemandedElts, in SimplifyDemandedVectorElts()
3068 if (!DemandedElts[0]) { in SimplifyDemandedVectorElts()
3108 return SimplifyDemandedVectorElts(Src, DemandedElts, KnownUndef, in SimplifyDemandedVectorElts()
3117 SrcDemandedElts = APIntOps::ScaleBitMask(DemandedElts, NumSrcElts); in SimplifyDemandedVectorElts()
3129 if (DemandedElts[i]) { in SimplifyDemandedVectorElts()
3149 if (DemandedElts[Elt]) in SimplifyDemandedVectorElts()
3172 SrcDemandedElts = APIntOps::ScaleBitMask(DemandedElts, NumSrcElts); in SimplifyDemandedVectorElts()
3180 if (DemandedElts[i]) { in SimplifyDemandedVectorElts()
3192 if (!DemandedElts.isAllOnes()) { in SimplifyDemandedVectorElts()
3199 if (!DemandedElts[i] && !Ops[i].isUndef()) { in SimplifyDemandedVectorElts()
3226 APInt SubElts = DemandedElts.extractBits(NumSubElts, i * NumSubElts); in SimplifyDemandedVectorElts()
3236 if (!DemandedElts.isAllOnes()) { in SimplifyDemandedVectorElts()
3241 APInt SubElts = DemandedElts.extractBits(NumSubElts, i * NumSubElts); in SimplifyDemandedVectorElts()
3262 APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx); in SimplifyDemandedVectorElts()
3263 APInt DemandedSrcElts = DemandedElts; in SimplifyDemandedVectorElts()
3306 APInt DemandedSrcElts = DemandedElts.zext(NumSrcElts).shl(Idx); in SimplifyDemandedVectorElts()
3316 if (!DemandedElts.isAllOnes()) { in SimplifyDemandedVectorElts()
3336 if (!DemandedElts[Idx]) in SimplifyDemandedVectorElts()
3339 APInt DemandedVecElts(DemandedElts); in SimplifyDemandedVectorElts()
3352 if (SimplifyDemandedVectorElts(Vec, DemandedElts, VecUndef, VecZero, TLO, in SimplifyDemandedVectorElts()
3366 if (SimplifyDemandedVectorElts(Sel, DemandedElts, UndefSel, ZeroSel, TLO, in SimplifyDemandedVectorElts()
3371 APInt DemandedLHS(DemandedElts); in SimplifyDemandedVectorElts()
3372 APInt DemandedRHS(DemandedElts); in SimplifyDemandedVectorElts()
3387 APInt DemandedSel = DemandedElts & ~KnownZero; in SimplifyDemandedVectorElts()
3388 if (DemandedSel != DemandedElts) in SimplifyDemandedVectorElts()
3405 if (M < 0 || !DemandedElts[i]) in SimplifyDemandedVectorElts()
3432 if (!DemandedElts[i] || (M < (int)NumElts && UndefLHS[M]) || in SimplifyDemandedVectorElts()
3475 APInt DemandedSrcElts = DemandedElts.zext(NumSrcElts); in SimplifyDemandedVectorElts()
3491 if (DemandedElts.isSubsetOf(KnownUndef)) in SimplifyDemandedVectorElts()
3524 if (SimplifyDemandedVectorElts(Op0, DemandedElts, UndefLHS, ZeroLHS, TLO, in SimplifyDemandedVectorElts()
3542 if (SimplifyDemandedVectorElts(Op1, DemandedElts, UndefRHS, ZeroRHS, TLO, in SimplifyDemandedVectorElts()
3546 if (SimplifyDemandedVectorElts(Op0, DemandedElts, UndefLHS, ZeroLHS, TLO, in SimplifyDemandedVectorElts()
3555 if (!DemandedElts.isAllOnes()) in SimplifyDemandedVectorElts()
3569 if (SimplifyDemandedVectorElts(Op1, DemandedElts, UndefRHS, ZeroRHS, TLO, in SimplifyDemandedVectorElts()
3573 if (SimplifyDemandedVectorElts(Op0, DemandedElts, UndefLHS, ZeroLHS, TLO, in SimplifyDemandedVectorElts()
3582 if (!DemandedElts.isAllOnes()) in SimplifyDemandedVectorElts()
3595 if (SimplifyDemandedVectorElts(Op1, DemandedElts, SrcUndef, SrcZero, TLO, in SimplifyDemandedVectorElts()
3600 APInt DemandedElts0 = DemandedElts & ~SrcZero; in SimplifyDemandedVectorElts()
3611 if (DemandedElts.isSubsetOf(SrcZero | KnownZero | SrcUndef | KnownUndef)) in SimplifyDemandedVectorElts()
3623 if (!DemandedElts.isAllOnes()) in SimplifyDemandedVectorElts()
3631 if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, KnownUndef, in SimplifyDemandedVectorElts()
3637 if (DemandedElts.isSubsetOf(KnownUndef)) in SimplifyDemandedVectorElts()
3644 if (SimplifyDemandedVectorEltsForTargetNode(Op, DemandedElts, KnownUndef, in SimplifyDemandedVectorElts()
3661 if (DemandedElts.isSubsetOf(KnownUndef)) in SimplifyDemandedVectorElts()
3671 const APInt &DemandedElts, in computeKnownBitsForTargetNode() argument
3685 const APInt &DemandedElts, const MachineRegisterInfo &MRI, in computeKnownBitsForTargetInstr() argument
3718 GISelKnownBits &Analysis, Register R, const APInt &DemandedElts, in computeNumSignBitsForTargetInstr() argument
3724 SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, in SimplifyDemandedVectorEltsForTargetNode() argument
3736 SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, in SimplifyDemandedBitsForTargetNode() argument
3744 computeKnownBitsForTargetNode(Op, Known, DemandedElts, TLO.DAG, Depth); in SimplifyDemandedBitsForTargetNode()
3749 SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, in SimplifyMultipleUseDemandedBitsForTargetNode() argument
3783 SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, in isGuaranteedNotToBeUndefOrPoisonForTargetNode() argument
3796 SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, in canCreateUndefOrPoisonForTargetNode() argument
3822 const APInt &DemandedElts, in isSplatValueForTargetNode() argument