Lines Matching refs:DCI
615 DAGCombinerInfo &DCI) const { in SimplifyDemandedBits()
616 SelectionDAG &DAG = DCI.DAG; in SimplifyDemandedBits()
617 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedBits()
618 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedBits()
623 DCI.AddToWorklist(Op.getNode()); in SimplifyDemandedBits()
624 DCI.CommitTargetLoweringOpt(TLO); in SimplifyDemandedBits()
631 DAGCombinerInfo &DCI) const { in SimplifyDemandedBits()
632 SelectionDAG &DAG = DCI.DAG; in SimplifyDemandedBits()
633 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedBits()
634 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedBits()
640 DCI.AddToWorklist(Op.getNode()); in SimplifyDemandedBits()
641 DCI.CommitTargetLoweringOpt(TLO); in SimplifyDemandedBits()
2939 DAGCombinerInfo &DCI) const { in SimplifyDemandedVectorElts()
2940 SelectionDAG &DAG = DCI.DAG; in SimplifyDemandedVectorElts()
2941 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedVectorElts()
2942 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedVectorElts()
2948 DCI.AddToWorklist(Op.getNode()); in SimplifyDemandedVectorElts()
2949 DCI.CommitTargetLoweringOpt(TLO); in SimplifyDemandedVectorElts()
3914 DAGCombinerInfo &DCI) const { in foldSetCCWithAnd()
3918 SelectionDAG &DAG = DCI.DAG; in foldSetCCWithAnd()
3981 if (DCI.isBeforeLegalizeOps() || in foldSetCCWithAnd()
4016 EVT SCCVT, SDValue N0, SDValue N1, ISD::CondCode Cond, DAGCombinerInfo &DCI, in optimizeSetCCOfSignedTruncationCheck() argument
4085 SelectionDAG &DAG = DCI.DAG; in optimizeSetCCOfSignedTruncationCheck()
4106 DAGCombinerInfo &DCI, const SDLoc &DL) const { in optimizeSetCCByHoistingAndByConstFromLogicalShift() argument
4115 SelectionDAG &DAG = DCI.DAG; in optimizeSetCCByHoistingAndByConstFromLogicalShift()
4178 DAGCombinerInfo &DCI) const { in foldSetCCWithBinOp()
4187 SelectionDAG &DAG = DCI.DAG; in foldSetCCWithBinOp()
4208 !DCI.isBeforeLegalize()); in foldSetCCWithBinOp()
4211 if (!DCI.isCalledByLegalizer()) in foldSetCCWithBinOp()
4212 DCI.AddToWorklist(YShl1.getNode()); in foldSetCCWithBinOp()
4403 DAGCombinerInfo &DCI, in SimplifySetCC() argument
4405 SelectionDAG &DAG = DCI.DAG; in SimplifySetCC()
4425 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4434 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4503 DCI.isBeforeLegalize() && N0->hasOneUse()) { in SimplifySetCC()
4590 if (DCI.isBeforeLegalize() && in SimplifySetCC()
4684 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4718 if (!DCI.isCalledByLegalizer()) in SimplifySetCC()
4719 DCI.AddToWorklist(ZextOp.getNode()); in SimplifySetCC()
4737 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4837 optimizeSetCCOfSignedTruncationCheck(VT, N0, N1, Cond, DCI, dl)) in SimplifySetCC()
4866 if ((DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4886 if ((DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4902 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { in SimplifySetCC()
4920 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { in SimplifySetCC()
4937 VT, N0, N1, Cond, DCI, dl)) in SimplifySetCC()
5005 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { in SimplifySetCC()
5042 getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize()); in SimplifySetCC()
5068 EVT ShiftTy = getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize()); in SimplifySetCC()
5129 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
5190 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
5276 if (SDValue V = foldSetCCWithBinOp(VT, N0, N1, Cond, dl, DCI)) in SimplifySetCC()
5282 if (SDValue V = foldSetCCWithBinOp(VT, N1, N0, Cond, dl, DCI)) in SimplifySetCC()
5285 if (SDValue V = foldSetCCWithAnd(VT, N0, N1, Cond, dl, DCI)) in SimplifySetCC()
5296 if (SDValue Folded = buildUREMEqFold(VT, N0, N1, Cond, DCI, dl)) in SimplifySetCC()
5299 if (SDValue Folded = buildSREMEqFold(VT, N0, N1, Cond, DCI, dl)) in SimplifySetCC()
5313 if (!DCI.isCalledByLegalizer()) in SimplifySetCC()
5314 DCI.AddToWorklist(Temp.getNode()); in SimplifySetCC()
5323 if (!DCI.isCalledByLegalizer()) in SimplifySetCC()
5324 DCI.AddToWorklist(Temp.getNode()); in SimplifySetCC()
5330 if (!DCI.isCalledByLegalizer()) in SimplifySetCC()
5331 DCI.AddToWorklist(Temp.getNode()); in SimplifySetCC()
5337 if (!DCI.isCalledByLegalizer()) in SimplifySetCC()
5338 DCI.AddToWorklist(Temp.getNode()); in SimplifySetCC()
5347 if (!DCI.isCalledByLegalizer()) in SimplifySetCC()
5348 DCI.AddToWorklist(N0.getNode()); in SimplifySetCC()
5393 DAGCombinerInfo &DCI) const { in PerformDAGCombine()
6545 DAGCombinerInfo &DCI, in buildUREMEqFold() argument
6549 DCI, DL, Built)) { in buildUREMEqFold()
6551 DCI.AddToWorklist(N); in buildUREMEqFold()
6561 DAGCombinerInfo &DCI, const SDLoc &DL, in prepareUREMEqFold() argument
6571 SelectionDAG &DAG = DCI.DAG; in prepareUREMEqFold()
6575 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout(), !DCI.isBeforeLegalize()); in prepareUREMEqFold()
6579 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::MUL, VT)) in prepareUREMEqFold()
6716 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::SUB, VT)) in prepareUREMEqFold()
6731 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ROTR, VT)) in prepareUREMEqFold()
6788 DAGCombinerInfo &DCI, in buildSREMEqFold() argument
6792 DCI, DL, Built)) { in buildSREMEqFold()
6795 DCI.AddToWorklist(N); in buildSREMEqFold()
6805 DAGCombinerInfo &DCI, const SDLoc &DL, in prepareSREMEqFold() argument
6820 SelectionDAG &DAG = DCI.DAG; in prepareSREMEqFold()
6824 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout(), !DCI.isBeforeLegalize()); in prepareSREMEqFold()
6829 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::MUL, VT)) in prepareSREMEqFold()
6984 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ADD, VT)) in prepareSREMEqFold()
6996 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ROTR, VT)) in prepareSREMEqFold()