225     Topo.AddPredQueued(SU, D.getSUnit());  in AddPredQueued()
233     Topo.AddPred(SU, D.getSUnit());  in AddPred()
241     Topo.RemovePred(SU, D.getSUnit());  in RemovePred()
401   SUnit *PredSU = PredEdge->getSUnit();  in ReleasePred()
566       assert((!RegDef || RegDef == SU || RegDef == Pred.getSUnit()) &&  in ReleasePredecessors()
568       LiveRegDefs[Pred.getReg()] = Pred.getSUnit();  in ReleasePredecessors()
823   SUnit *PredSU = PredEdge->getSUnit();  in CapturePred()
845       assert(LiveRegDefs[Pred.getReg()] == Pred.getSUnit() &&  in UnscheduleNodeBottomUp()
901         LiveRegGens[Reg] = Succ.getSUnit();  in UnscheduleNodeBottomUp()
904               Succ2.getSUnit()->getHeight() < LiveRegGens[Reg]->getHeight())  in UnscheduleNodeBottomUp()
905             LiveRegGens[Reg] = Succ2.getSUnit();  in UnscheduleNodeBottomUp()
1062     else if (isOperandOf(Pred.getSUnit(), LoadNode))  in TryUnfoldSU()
1090     SUnit *SuccDep = D.getSUnit();  in TryUnfoldSU()
1101     SUnit *SuccDep = D.getSUnit();  in TryUnfoldSU()
1198     SUnit *SuccSU = Succ.getSUnit();  in CopyAndMoveSuccessors()
1237     SUnit *SuccSU = Succ.getSUnit();  in InsertCopiesAndMoveSuccs()
1359       CheckForLiveRegDef(Pred.getSUnit(), Pred.getReg(), LiveRegDefs.get(),  in DelayForLiveRegsBottomUp()
1973       SUnit *PredSU = Pred.getSUnit();  in CalcNodeSethiUllmanNumber()
1996       SUnit *PredSU = Pred.getSUnit();  in CalcNodeSethiUllmanNumber()
2100     SUnit *PredSU = Pred.getSUnit();  in HighRegPressure()
2149     SUnit *PredSU = Pred.getSUnit();  in RegPressureDiff()
2192     SUnit *PredSU = Pred.getSUnit();  in scheduledNode()
2274     SUnit *PredSU = Pred.getSUnit();  in unscheduledNode()
2350     unsigned Height = Succ.getSUnit()->getHeight();  in closestSucc()
2353     if (Succ.getSUnit()->getNode() &&  in closestSucc()
2354         Succ.getSUnit()->getNode()->getOpcode() == ISD::CopyToReg)  in closestSucc()
2355       Height = closestSucc(Succ.getSUnit())+1;  in closestSucc()
2379     const SUnit *PredSU = Pred.getSUnit();  in hasOnlyLiveInOpers()
2401     const SUnit *SuccSU = Succ.getSUnit();  in hasOnlyLiveOutUses()
2438     Pred.getSUnit()->isVRegCycle = true;  in initVRegCycle()
2450     SUnit *PredSU = Pred.getSUnit();  in resetVRegCycle()
2454       Pred.getSUnit()->isVRegCycle = false;  in resetVRegCycle()
2468     if (Pred.getSUnit()->isVRegCycle &&  in hasVRegCycleUse()
2469         Pred.getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) {  in hasVRegCycleUse()
2867     SUnit *SuccSU = Succ.getSUnit();  in canClobberReachingPhysRegUse()
2874           scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit()))  in canClobberReachingPhysRegUse()
2882             scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit()))  in canClobberReachingPhysRegUse()
2976       if (Pred.isCtrl() && Pred.getSUnit()) {  in PrescheduleNodesWithMultipleUses()
2978         SDNode *PredND = Pred.getSUnit()->getNode();  in PrescheduleNodesWithMultipleUses()
3001         PredSU = Pred.getSUnit();  in PrescheduleNodesWithMultipleUses()
3022       SUnit *PredSuccSU = PredSucc.getSUnit();  in PrescheduleNodesWithMultipleUses()
3046       SUnit *SuccSU = Edge.getSUnit();  in PrescheduleNodesWithMultipleUses()
3093         SUnit *SuccSU = Succ.getSUnit();  in AddPseudoTwoAddrDeps()
3109           SuccSU = SuccSU->Succs.front().getSUnit();  in AddPseudoTwoAddrDeps()