Lines Matching refs:SUnit
150 std::vector<SUnit *> PendingQueue;
169 std::unique_ptr<SUnit*[]> LiveRegDefs;
170 std::unique_ptr<SUnit*[]> LiveRegGens;
174 SmallVector<SUnit*, 4> Interferences;
176 using LRegsMapT = DenseMap<SUnit *, SmallVector<unsigned, 4>>;
186 DenseMap<SUnit*, SUnit*> CallSeqEndForStart;
211 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { in IsReachable()
217 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { in WillCreateCycle()
224 void AddPredQueued(SUnit *SU, const SDep &D) { in AddPredQueued()
232 void AddPred(SUnit *SU, const SDep &D) { in AddPred()
240 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred()
246 bool isReady(SUnit *SU) { in isReady()
251 void ReleasePred(SUnit *SU, const SDep *PredEdge);
252 void ReleasePredecessors(SUnit *SU);
255 void AdvancePastStalls(SUnit *SU);
256 void EmitNode(SUnit *SU);
257 void ScheduleNodeBottomUp(SUnit*);
259 void UnscheduleNodeBottomUp(SUnit*);
261 void BacktrackBottomUp(SUnit*, SUnit*);
262 SUnit *TryUnfoldSU(SUnit *);
263 SUnit *CopyAndMoveSuccessors(SUnit*);
264 void InsertCopiesAndMoveSuccs(SUnit*, unsigned,
267 SmallVectorImpl<SUnit*>&);
268 bool DelayForLiveRegsBottomUp(SUnit*, SmallVectorImpl<unsigned>&);
272 SUnit *PickNodeToScheduleBottomUp();
276 SUnit *CreateNewSUnit(SDNode *N) { in CreateNewSUnit()
278 SUnit *NewNode = newSUnit(N); in CreateNewSUnit()
286 SUnit *CreateClone(SUnit *N) { in CreateClone()
288 SUnit *NewNode = Clone(N); in CreateClone()
367 LiveRegDefs.reset(new SUnit*[TRI->getNumRegs() + 1]()); in Schedule()
368 LiveRegGens.reset(new SUnit*[TRI->getNumRegs() + 1]()); in Schedule()
400 void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) { in ReleasePred()
401 SUnit *PredSU = PredEdge->getSUnit(); in ReleasePred()
556 void ScheduleDAGRRList::ReleasePredecessors(SUnit *SU) { in ReleasePredecessors()
565 SUnit *RegDef = LiveRegDefs[Pred.getReg()]; (void)RegDef; in ReleasePredecessors()
589 SUnit *Def = &SUnits[N->getNodeId()]; in ReleasePredecessors()
653 void ScheduleDAGRRList::AdvancePastStalls(SUnit *SU) { in AdvancePastStalls()
695 void ScheduleDAGRRList::EmitNode(SUnit *SU) { in EmitNode()
733 static void resetVRegCycle(SUnit *SU);
738 void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU) { in ScheduleNodeBottomUp()
823 SUnit *PredSU = PredEdge->getSUnit(); in CapturePred()
837 void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) { in UnscheduleNodeBottomUp()
861 SUnit *SeqEnd = CallSeqEndForStart[SU]; in UnscheduleNodeBottomUp()
937 std::vector<SUnit *>::const_iterator I = (Sequence.end() - LookAhead); in RestoreHazardCheckerBottomUp()
940 SUnit *SU = *I; in RestoreHazardCheckerBottomUp()
950 void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, SUnit *BtSU) { in BacktrackBottomUp()
951 SUnit *OldSU = Sequence.back(); in BacktrackBottomUp()
972 static bool isOperandOf(const SUnit *SU, SDNode *N) { in isOperandOf()
982 SUnit *ScheduleDAGRRList::TryUnfoldSU(SUnit *SU) { in TryUnfoldSU()
1000 SUnit *LoadSU; in TryUnfoldSU()
1017 SUnit *NewSU; in TryUnfoldSU()
1090 SUnit *SuccDep = D.getSUnit(); in TryUnfoldSU()
1101 SUnit *SuccDep = D.getSUnit(); in TryUnfoldSU()
1131 SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { in CopyAndMoveSuccessors()
1148 SUnit *NewSU; in CopyAndMoveSuccessors()
1170 SUnit *UnfoldSU = TryUnfoldSU(SU); in CopyAndMoveSuccessors()
1194 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps; in CopyAndMoveSuccessors()
1198 SUnit *SuccSU = Succ.getSUnit(); in CopyAndMoveSuccessors()
1219 void ScheduleDAGRRList::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, in InsertCopiesAndMoveSuccs()
1222 SmallVectorImpl<SUnit*> &Copies) { in InsertCopiesAndMoveSuccs()
1223 SUnit *CopyFromSU = CreateNewSUnit(nullptr); in InsertCopiesAndMoveSuccs()
1227 SUnit *CopyToSU = CreateNewSUnit(nullptr); in InsertCopiesAndMoveSuccs()
1233 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps; in InsertCopiesAndMoveSuccs()
1237 SUnit *SuccSU = Succ.getSUnit(); in InsertCopiesAndMoveSuccs()
1295 static void CheckForLiveRegDef(SUnit *SU, unsigned Reg, SUnit **LiveRegDefs, in CheckForLiveRegDef()
1321 static void CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask, in CheckForLiveRegDefMasked()
1322 ArrayRef<SUnit*> LiveRegDefs, in CheckForLiveRegDefMasked()
1348 DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) { in DelayForLiveRegsBottomUp()
1445 SUnit *SU = Interferences[i-1]; in releaseInterferences()
1471 SUnit *ScheduleDAGRRList::PickNodeToScheduleBottomUp() { in PickNodeToScheduleBottomUp()
1472 SUnit *CurSU = AvailableQueue->empty() ? nullptr : AvailableQueue->pop(); in PickNodeToScheduleBottomUp()
1507 for (SUnit *TrySU : Interferences) { in PickNodeToScheduleBottomUp()
1512 SUnit *BtSU = nullptr; in PickNodeToScheduleBottomUp()
1558 SUnit *TrySU = Interferences[0]; in PickNodeToScheduleBottomUp()
1562 SUnit *LRDef = LiveRegDefs[Reg]; in PickNodeToScheduleBottomUp()
1575 SUnit *NewDef = nullptr; in PickNodeToScheduleBottomUp()
1583 SmallVector<SUnit*, 2> Copies; in PickNodeToScheduleBottomUp()
1610 SUnit *RootSU = &SUnits[DAG->getRoot().getNode()->getNodeId()]; in ListScheduleBottomUp()
1625 SUnit *SU = PickNodeToScheduleBottomUp(); in ListScheduleBottomUp()
1652 bool isReady(SUnit* SU, unsigned CurCycle) const { return true; } in isReady()
1662 bool operator()(SUnit* left, SUnit* right) const { in operator ()()
1682 bool operator()(SUnit* left, SUnit* right) const;
1696 bool operator()(SUnit* left, SUnit* right) const;
1710 bool isReady(SUnit *SU, unsigned CurCycle) const;
1712 bool operator()(SUnit* left, SUnit* right) const;
1727 bool isReady(SUnit *SU, unsigned CurCycle) const;
1729 bool operator()(SUnit* left, SUnit* right) const;
1734 std::vector<SUnit *> Queue;
1740 std::vector<SUnit> *SUnits = nullptr;
1787 void initNodes(std::vector<SUnit> &sunits) override;
1789 void addNode(const SUnit *SU) override;
1791 void updateNode(const SUnit *SU) override;
1799 unsigned getNodePriority(const SUnit *SU) const;
1801 unsigned getNodeOrdering(const SUnit *SU) const { in getNodeOrdering()
1809 void push(SUnit *U) override { in push()
1815 void remove(SUnit *SU) override { in remove()
1818 std::vector<SUnit *>::iterator I = llvm::find(Queue, SU); in remove()
1829 bool HighRegPressure(const SUnit *SU) const;
1831 bool MayReduceRegPressure(SUnit *SU) const;
1833 int RegPressureDiff(SUnit *SU, unsigned &LiveUses) const;
1835 void scheduledNode(SUnit *SU) override;
1837 void unscheduledNode(SUnit *SU) override;
1840 bool canClobber(const SUnit *SU, const SUnit *Op);
1847 static SUnit *popFromQueueImpl(std::vector<SUnit *> &Q, SF &Picker) { in popFromQueueImpl()
1855 SUnit *V = Q[BestIdx]; in popFromQueueImpl()
1863 SUnit *popFromQueue(std::vector<SUnit *> &Q, SF &Picker, ScheduleDAG *DAG) { in popFromQueue()
1898 bool isReady(SUnit *U) const override { in isReady()
1902 SUnit *pop() override { in pop()
1905 SUnit *V = popFromQueue(Queue, Picker, scheduleDAG); in pop()
1913 std::vector<SUnit *> DumpQueue = Queue; in dump()
1916 SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG); in dump()
1941 static int checkSpecialNodes(const SUnit *left, const SUnit *right) { in checkSpecialNodes()
1952 CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) { in CalcNodeSethiUllmanNumber()
1958 WorkState(const SUnit *SU) : SU(SU) {} in CalcNodeSethiUllmanNumber()
1959 const SUnit *SU; in CalcNodeSethiUllmanNumber()
1973 SUnit *PredSU = Pred.getSUnit(); in CalcNodeSethiUllmanNumber()
1996 SUnit *PredSU = Pred.getSUnit(); in CalcNodeSethiUllmanNumber()
2022 for (const SUnit &SU : *SUnits) in CalculateSethiUllmanNumbers()
2026 void RegReductionPQBase::addNode(const SUnit *SU) { in addNode()
2033 void RegReductionPQBase::updateNode(const SUnit *SU) { in updateNode()
2040 unsigned RegReductionPQBase::getNodePriority(const SUnit *SU) const { in getNodePriority()
2093 bool RegReductionPQBase::HighRegPressure(const SUnit *SU) const { in HighRegPressure()
2100 SUnit *PredSU = Pred.getSUnit(); in HighRegPressure()
2118 bool RegReductionPQBase::MayReduceRegPressure(SUnit *SU) const { in MayReduceRegPressure()
2143 int RegReductionPQBase::RegPressureDiff(SUnit *SU, unsigned &LiveUses) const { in RegPressureDiff()
2149 SUnit *PredSU = Pred.getSUnit(); in RegPressureDiff()
2182 void RegReductionPQBase::scheduledNode(SUnit *SU) { in scheduledNode()
2192 SUnit *PredSU = Pred.getSUnit(); in scheduledNode()
2251 void RegReductionPQBase::unscheduledNode(SUnit *SU) { in unscheduledNode()
2274 SUnit *PredSU = Pred.getSUnit(); in unscheduledNode()
2346 static unsigned closestSucc(const SUnit *SU) { in closestSucc()
2364 static unsigned calcMaxScratches(const SUnit *SU) { in calcMaxScratches()
2375 static bool hasOnlyLiveInOpers(const SUnit *SU) { in hasOnlyLiveInOpers()
2379 const SUnit *PredSU = Pred.getSUnit(); in hasOnlyLiveInOpers()
2397 static bool hasOnlyLiveOutUses(const SUnit *SU) { in hasOnlyLiveOutUses()
2401 const SUnit *SuccSU = Succ.getSUnit(); in hasOnlyLiveOutUses()
2425 static void initVRegCycle(SUnit *SU) { in initVRegCycle()
2444 static void resetVRegCycle(SUnit *SU) { in resetVRegCycle()
2450 SUnit *PredSU = Pred.getSUnit(); in resetVRegCycle()
2461 static bool hasVRegCycleUse(const SUnit *SU) { in hasVRegCycleUse()
2480 static bool BUHasStall(SUnit *SU, int Height, RegReductionPQBase *SPQ) { in BUHasStall()
2490 static int BUCompareLatency(SUnit *left, SUnit *right, bool checkPref, in BUCompareLatency()
2541 static bool BURRSort(SUnit *left, SUnit *right, RegReductionPQBase *SPQ) { in BURRSort()
2645 bool bu_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { in operator ()()
2653 bool src_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { in operator ()()
2672 bool hybrid_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const { in isReady()
2687 bool hybrid_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { in operator ()()
2719 bool ilp_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const { in isReady()
2729 static bool canEnableCoalescing(SUnit *SU) { in canEnableCoalescing()
2753 bool ilp_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { in operator ()()
2814 void RegReductionPQBase::initNodes(std::vector<SUnit> &sunits) { in initNodes()
2827 for (SUnit &SU : sunits) in initNodes()
2835 bool RegReductionPQBase::canClobber(const SUnit *SU, const SUnit *Op) { in canClobber()
2856 static bool canClobberReachingPhysRegUse(const SUnit *DepSU, const SUnit *SU, in canClobberReachingPhysRegUse()
2867 SUnit *SuccSU = Succ.getSUnit(); in canClobberReachingPhysRegUse()
2892 static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU, in canClobberPhysRegDefs()
2958 for (SUnit &SU : *SUnits) { in PrescheduleNodesWithMultipleUses()
2998 SUnit *PredSU = nullptr; in PrescheduleNodesWithMultipleUses()
3022 SUnit *PredSuccSU = PredSucc.getSUnit(); in PrescheduleNodesWithMultipleUses()
3046 SUnit *SuccSU = Edge.getSUnit(); in PrescheduleNodesWithMultipleUses()
3068 for (SUnit &SU : *SUnits) { in AddPseudoTwoAddrDeps()
3087 const SUnit *DUSU = &(*SUnits)[DU->getNodeId()]; in AddPseudoTwoAddrDeps()
3093 SUnit *SuccSU = Succ.getSUnit(); in AddPseudoTwoAddrDeps()